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PI74FCT377TQSOP

Description
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
File Size35KB,3 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
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PI74FCT377TQSOP Overview

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT377T
OCTAL D FLIP-FLOP with CLOCK ENABLE
PI74FCT377T
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Product Features:
• The PI74FCT377T is pin compatible with bipolar FAST™
Series at a higher speed and lower power
consumption
• TTL input and output levels
• Octal D flip-flops with Clock Enable
• Extremely low static power
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 20-pin 173 mil wide plastic TSSOP (L)
– 20-pin 300 mil wide plastic DIP (P)
– 20-pin 150 mil wide plastic QSOP (Q)
– 20-pin 150 mil wide plastic TQSOP (R)
– 20-pin 300 mil wide plastic SOIC (S)
Fast CMOS Octal D Flip-Flop
with Clock Enable
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6/0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT377T is an 8-bit wide octal designed with eight edge-
triggered D-type flip-flops with individual D inputs and O outputs.
When Clock Enable (CE) is LOW, the common buffered Clock
(CP) loads all flip-flops simultaneously. The register is fully edge-
triggered. D input state, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s O
output. The CE input must be stable only one setup time prior to
the LOW-to-HIGH transition for predictable operation.
Logic Block Diagram
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Product Pin Configuration
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
20
2
19
3
20-PIN
18
L20
17
4
P20
16
5
Q20
6
15
R20
7
14
S20
8
13
9
12
10
11
Product Pin Description
Pin Name
CE
CP
D
0
-D
7
O
0
-O
7
GND
V
CC
Truth Table
(1)
Vcc
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
Inputs
Outputs
Description
Mode
CP
CE
D
N
O
N
Clock Enable (Active LOW)
Load "1"
l
h
H
Clock Pulse Input
Load "0"
l
l
L
Data Inputs
Hold
h
X
NC
Data Outputs
(Do Nothing)
H
H
X
NC
Ground
Power
1. H = HIGH Voltage Level
h = HIGH Voltage Level one setup time
prior to the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level
l = LOW Voltage Level one setup time
prior to the LOW-to-HIGH Clock
Transition
X = Don't Care
NC = No Change
= LOW-to-HIGH Clock Transition
1
PS2017A 03/11/96

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