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PI29FCT2520T

Description
FAST CMOS MULTILEVEL PIPELINE REGISTERS
File Size47KB,5 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
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PI29FCT2520T Overview

FAST CMOS MULTILEVEL PIPELINE REGISTERS

FCT520.pm6
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32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520T/2520T
PI29FCT521T
Fast CMOS Multilevel Pipeline Registers
Product Features:
• PI29FCT520T and PI29FCT521T are pinout and
function compatible with IDT29FCT520/521,
QS29FCT520/521 and AMD's Am29520/521
• Four 8-bit high-speed registers
• Hold, Transfer, and load instructions
• Dual two-level or single four-level pipeline operation
• TTL input and output levels, reducing problematic
"ground bounce"
• High output drive
I
OL
= 48 mA
• Extremely low static power (1 mW, typ.)
• Industrial operating temperature range: –40°C to +85°C
• FCT (2xxxT) has a 25Ω series resistor.
• Packages available:
– 24-pin 300 mil wide plastic DIP (P24)
– 24-pin 150 mil wide plastic QSOP (Q24)
– 24-pin 150 mil wide plastic TQSOP (R24)
– 24-pin 300 mil wide plastic SOIC (S24)
Product Description:
Pericom Semiconductor’s PI29FCT series of logic circuits are
pro-duced in the Company’s advanced 0.8 micron CMOS
technology, achieving industry leading speed grades.
The PI29FCT520T/2520T and PI29FCT521T are multilevel
pipeline registers containing four 8-bit positive triggered registers
which can be configured as a dual 2-level or a single 4-level
pipeline. These products are designed for use as temporary storage
or for storage delays in pipelined systems.
The PI29FCT521T differs from the PI29FCT520T/2520T only in
the way data is loaded into and between registers in the dual 2-level
operation. When data is entered into the first level (I = 2 or I = 1)
of the PI29FCT520T/2520T, the existing data in the first level is
moved to the second level. In the PI29FCT521T, these instructions
simply overwrite the data in the first level. Transfer of data to the
second level is achieved using the 4-level shift instruction (I = 0)
causing the first level to change. In either part, I = 3 shift
instruction puts the registers on hold.
Device models available upon request.
Logic Block Diagram
D
0
–D
7
8
MUX
2
I
0
,I
1
REGISTER
CONTROL
1
CLK
OCTAL
REGISTER A1
OCTAL
REGISTER B1
OCTAL
REGISTER A2
OCTAL
REGISTER B2
S
0
,S
1
2
MUX
OE
8
Y
0
–Y
7
1
PS2002B 12/10/96
1
12/18/96, 4:44 PM

PI29FCT2520T Related Products

PI29FCT2520T PI29FCT521T PI29FCT520T
Description FAST CMOS MULTILEVEL PIPELINE REGISTERS FAST CMOS MULTILEVEL PIPELINE REGISTERS FAST CMOS MULTILEVEL PIPELINE REGISTERS
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