VSC880 datasheet, PDF - EEWORLD Datasheet

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VSC880: DescriptionHigh Performance 16x16 Serial Crosspoint Switch; CategoryWireless rf/communication Telecom circuit; File Size380KB，28 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC880 Overview

High Performance 16x16 Serial Crosspoint Switch

VSC880 Parametric

Parameter Name	Attribute value
Maker	Vitesse Semiconductor Corporation
Parts packaging code	BGA
package instruction	BGA,
Contacts	304
Reach Compliance Code	compli
JESD-30 code	R-PBGA-B304
Number of functions	1
Number of terminals	304
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Certification status	Not Qualified
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal location	BOTTOM

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

Features

• 16x16 Synchronous Serial Crosspoint Switch

• Serial Data Rates: 2.0Gb/s

• 32Gb/s Aggregate Data Bandwidth

• Parallel Switches Can Increase Data Bandwidth in

Multiples of 32Gb/s

• Designed in Conjunction with the VSC870

Backplane Transceiver

• Automatic Word and Cell Synchronization to the

Transceiver

• Two Modes of Operation: Distributed Control

Self-routing

Packet Mode

and Central Control

Cell Mode

• Multicast Supported in All Modes

High Performance 16x16

Serial Crosspoint Switch

• Supports Variable Length Packets in Packet

Mode

• Built-in Flow Control Channel in Packet Mode

• Supports Cell Synchronization in Cell Mode

• Parallel CPU Interface and Parallel Switch

Configuration Interface

• Loopback, Built-in Self Test and Scan Functions

• 5V Tolerant TTL Inputs

• Dual 3.3V/2.5V or Dual 3.3V/2.0V Power

Supplies

• Serial Port Quadrants Can be Powered Down

• Available in 304 BGA Package

VSC880 Block Diagram

Serial Port (16x)

TXS+/TXS-

Switch Matrix

Parallel

Serial

VSCTE

VSCIPNC

VSCOPNC

MEN

FACLPBK

CMODE

TESTEN

SCANIN

SCANOUT

Port

Logic

RXS+/RXS-

DRU

Serial

Parallel

WCLK

REFCLK

TCLKEN

LOCKDET

CCLK

RESET

BSTLPBK

BSTEN

BSTRST

BSTPASS

Arbitration Logic

and Switch Control

Registers

CEN

DATA[15:0]

FI[3:0]

WEN

CMU

Clock

Gen

ADDR[5:0]

Status and

Control Registers

CDATA[7:0]

CWEN

CSEL

INT

RESYNEN

BIST Logic

G52191-0, Rev 4.2

01/05/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC880

1.1.2 Data Scrambling

High Performance 16x16

Serial Crosspoint Switch

To allow the VSC870 CRU to recover the bit clock, a 15% edge transition density must be guaranteed on the

serial data links. All command words and connection request words contain this required density. In order to get this

density on data words, scrambling must be employed by the transceiver (see VSC870 data sheet).

1.1.3 Bit Synchronization

In Packet Mode and Cell Mode, the switch acts as the source of the bit clock. It multiplies the local 62.5MHz

reference clock by 34 to generate a 2.125GHz clock and uses this clock to serialize the 32-bit word and 2 overhead

bits. The transceiver receives and feeds this serial data stream to a digital CRU to recover the bit clock and

deserialize the data stream to a 32-bit word plus 2 overhead bits at 62.5MHz. The transceiver also uses this recovered

clock to serialize its transmit words that are sent to the switch. In this way, the switch and all the transceivers are

frequency-locked to one clock source which is provided by the reference clock on the switch card. Because of this,

the switch chip needs to recover only the phase information on the serial receive channel using a data recovery unit

(DRU). The DRU is designed as a delay lock loop and remains phase-locked to the incoming data stream as long as

the temperature does not change by more than 20°C after link initialization. If this temperature variation is exceeded,

a link error may occur causing the link to reinitialize. Because of this, system reset should be held until the system

reaches temperature stability before starting the link initializing process.

1.1.4 Word Synchronization

During power up or at reset, the transceiver can initiate the word synchronization process. First, the transceiver

sends reset patterns to the switch to request that the switch starts the initialization process. The switch, upon

receiving this request, will send out special ALIGN words. The transceiver receives this serial data stream and word

aligns to this ALIGN word by adjusting its own word boundary one bit at a time. Upon detecting the correct word

alignment, it starts the transmit word alignment process. In this process, the transceiver continuously sends ALIGN

words to the switch. The switch uses its own word clock (REFCLK) to detect this ALIGN word. If the transmitters

word is not aligned to the switch chip word clock when it arrives at the switch, the switch chip continues to send out

ALIGN words. After receiving 32 ALIGN words from the switch chip, the transceiver changes its transmit word

boundary by 1 bit position and repeats the process (this limits the distance from the transceiver to the switch to less

than 180ns one way). If the switch detects the transceivers ALIGN word correctly, it sends IDLE words to the

transceiver to signal that the transmitter has now word synchronized with the switch. It also clears the internal

registers LERR, TERR, DERR and CERR and sets the signal INT HIGH if all the enabled serial channels are

successfully initialized (see section 1.4).

1.1.5 Cell Synchronization

If CMODE is set HIGH, after the word synchronization process completes, the transceiver starts the cell

synchronization process. In this process, the transceiver detects the received cell clock (CCLK) sent from the switch

embedded in the alignment word. The switch delays the global cell clock to adjust out the pipeline delay from the

transceiver to the switch. The switch chip does this by connecting each port to itself during link initialization. By

sending an ALIGN words to itself, the transceiver can adjust the transmit clock until it is properly phase shifted

relative to the global cell clock. If cells are sent from the transceiver aligned to this transmit cell clock, they will

arrive at the switch aligned to the master cell clock which is originated at the switch. For this alignment process to

work, the minimum cell size is 8 words (32 bytes).

G52191-0, Rev 4.2

01/05/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 5

VSC880 Related Products

	VSC880	VSC880TY
Description	High Performance 16x16 Serial Crosspoint Switch	High Performance 16x16 Serial Crosspoint Switch
Maker	Vitesse Semiconductor Corporation	Vitesse Semiconductor Corporation
Parts packaging code	BGA	BGA
package instruction	BGA,	HBGA,
Contacts	304	304
Reach Compliance Code	compli	compli
JESD-30 code	R-PBGA-B304	S-PBGA-B304
Number of functions	1	1
Number of terminals	304	304
Maximum operating temperature	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	HBGA
Package shape	RECTANGULAR	SQUARE
Package form	GRID ARRAY	GRID ARRAY, HEAT SINK/SLUG
Certification status	Not Qualified	Not Qualified
Nominal supply voltage	3.3 V	2 V
surface mount	YES	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH	DIGITAL TIME SWITCH
Temperature level	COMMERCIAL	OTHER
Terminal form	BALL	BALL
Terminal location	BOTTOM	BOTTOM

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