Freescale Semiconductor
Technical Data
MC100ES6221
Rev 5, 04/2005
Low Voltage 1:20 Differential
ECL/PECL/HSTL Clock Fanout Buffer
The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6221
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver is high performance clock
distribution in computing, networking and telecommunication systems.
Features
•
•
•
•
•
•
•
•
•
•
•
1:20 differential clock fanout buffer
100 ps maximum device skew
SiGe technology
Supports DC to 2 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL/HSTL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 52 lead LQFP package with exposed pad for enhanced thermal
characteristics
Supports industrial temperature range
Pin and function compatible to the MC100EP221
52-lead Pb-free Package Available
MC100ES6221
LOW VOLTAGE DUAL
1:20 DIFFERENTIAL ECL/PECL/HSTL
CLOCK FANOUT BUFFER
TB SUFFIX
52-LEAD LQFP PACKAGE
EXPOSED PAD
CASE 1336A-01
Functional Description
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 1336A-01
The MC100ES6221 is designed for low skew clock distribution systems and
supports clock frequencies up to 2 GHz. The device accepts two clock sources.
The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals. The
selected input signal is distributed to 20 identical, differential ECL/PECL outputs. If V
BB
is connected to the CLK0 or CLK1 input
and bypassed to GND by a 10 nF capacitor, the MC100ES6221 can be driven by single-ended ECL/PECL signals utilizing the
V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6221 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6221 supports positive (PECL) and negative (ECL) supplies. The MC100ES6221 is pin and function compatible to the
MC100EP221.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Q9
Q10
Q10
Q11
Q11
Q0
Q0
V
CC
CLK0
CLK0
V
EE
V
CC
CLK1
CLK1
V
EE
CLK_SEL
0
1
Q1
Q1
Q2
Q2
Q3
Q3
V
CC
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
40
41
42
43
44
45
46
47
48
49
50
51
52
39 38 37 36
35 34 33 32 31 30 29 28 27
V
CC
26
25
24
23
22
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
V
CC
•
•
•
•
•
•
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
MC100ES6221
21
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10 11 12 13
V
CC
V
CC
CLK_SEL
CLK1
CLK0
CLK0
CLK1
Q19
Q19
V
EE
Figure 1. MC100ES6221 Logic Diagram
Table 1. Pin Configuration
Pin
CLK0, CLK0
CLK1, CLK1
CLK_SEL
QA[0–19], QA[0–19]
V
EE(1)
V
CC
V
BB
Input
Input
Input
Output
Supply
Supply
Output
DC
I/O
Type
ECL/PECL
HSTL
ECL/PECL
ECL/PECL
Figure 2. 52-Lead Package Pinout
(Top View)
Function
Differential reference clock signal input
Alternative differential reference clock signal input
Reference clock input select
Differential clock outputs
Negative power supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL and PECL operation
1. In ECL mode (negative power supply mode), V
EE
is either –3.3 V or –2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either
+3.3
V or
+2.5
V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
).
Table 2. Function Table
Pin
CLK_SEL
0
CLK0, CLK0 input pair is the reference clock. CLK0 can be
driven by ECL or PECL compatible signals.
1
CLK1, CLK1 input pair is the reference clock. CLK1 can be
driven by HSTL compatible signals.
MC100ES6221
2
Advanced Clock Drivers Devices
Freescale Semiconductor
Q18
Q18
V
BB
V
EE
V
BB
Table 3. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
FUNC
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Functional Temperature Range
–65
T
A
= –40
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+
0.3
V
CC
+
0.3
±20
±50
125
T
J
=
+110
Unit
V
V
V
mA
mA
°C
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 4. General Specifications
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
θ
JA
,
θ
JB
,
θ
JC
T
J
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
Input Capacitance
Thermal Resistance (junction-to-ambient,
junction-to-board, junction-to-case)
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
200
4000
2000
200
4.0
See
Table 9. Thermal Resistance
0
110
Min
Typ
V
CC
– 2
(1)
Max
Unit
V
V
V
V
mA
pF
°C/W
°C
Inputs
Condition
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MC100ES6221 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6221 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
MC100ES6221
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 5. PECL DC Characteristics
(V
CC
= 2.5 V
±
5% or V
CC
= 3.3 V
±
5%, V
EE
= GND, T
J
= 0°C to + 110°C)
Symbol
Characteristics
Differential Input Voltage
(2)
Differential Cross Point Voltage
(3)
Input Current
(1)
Differential Input Voltage
(5)
Differential Cross Point Voltage
(6)
Input High Voltage
Input Low Voltage
Input Current
Min
Typ
Max
Unit
Condition
Clock Input Pair CLK0, CLK0
(1)
(PECL differential signals)
V
PP
V
CMR
I
IN
V
DIF
V
X
V
IH
V
IL
I
IN
V
IH
V
IL
I
IN
V
OH
V
OL
I
EE(9)
V
BB
0.1
1.0
1.3
V
CC
– 0.3
±100
V
V
µA
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
Clock Input Pair CLK1, CLK1
(4)
(HSTL differential signals)
0.2
0
V
X
+
0.1
V
X
– 0.7
0.68 - 0.9
1.4
V
CC
– 0.7
V
X
+
0.7
V
X
– 0.1
±100
V
V
V
V
µA
V
IN
= V
X
±
0.2 V
Clock Inputs (PECL single ended signals)
Input Voltage High
Input Voltage Low
Input Current
(7)
V
CC
– 1.165
V
CC
– 1.810
V
CC
– 0.880
V
CC
– 1.475
±100
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(8)
I
OL
= –5 mA
(8)
V
EE
pins
I
BB
= 0.4 mA
PECL Clock Outputs (Q0–19, Q0–19)
Output High Voltage
Output Low Voltage
V
CC
– 1.1
V
CC
– 1.9
V
CC
– 1.005
V
CC
– 1.705
84
V
CC
– 1.42
V
CC
– 0.7
V
CC
– 1.4
160
V
CC
– 1.20
V
V
Supply current and V
BB
Maximum Quiescent Supply Current without
Output Termination Current
Output Reference Voltage (f
ref
< 1.0 GHz)
(10)
mA
V
1. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both
HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (V
CMR
).
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
4. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1.
5. V
DIF
(DC) is the minimum differential HSTL input voltage swing required for device functionality.
6. V
X
(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V
X
(DC)
range and the input swing lies within the V
PP
(DC) specification.
7. Inputs have internal pullup/pulldown resistors which affect the input current.
8. Equivalent to a termination of 50
Ω
to V
TT.
9. I
CC
calculation: I
CC
= (number of differential output used) x (I
OH
+
I
OL
)
+
I
EE
I
CC
= (number of differential output used) x (V
OH
– V
TT
)
÷
R
load
+
(V
OL
– V
TT
)
÷
R
load
+
I
EE
.
10. Using V
BB
to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only
differential input signals should be used with the MC100ES6221.
MC100ES6221
4
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. ECL DC Characteristics
(V
EE
=
–
2.5 V
±
5% or V
EE
=
–
3.3 V
±
5%, V
CC
= GND, T
J
= 0°C to + 110°C)
Symbol
Characteristics
Differential Input Voltage
(1)
Differential Cross Point Junction to top of
Package Voltage
(2)
Input Current
(1)
Min
Typ
Max
Unit
Condition
Clock Input Pair CLK0, CLK0 (ECL differential signals)
V
PP
V
CMR
I
IN
V
IH
V
IL
I
IN
V
OH
V
OL
I
EE(5)
V
BB
0.1
V
EE
+
1.0
1.3
–0.3
±100
V
V
µA
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
Clock Inputs (ECL single ended signals)
Input Voltage High
Input Voltage Low
Input Current
(3)
–1.165
–1.810
–0.880
–1.475
±100
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(4)
I
OL
= –5 mA
(4)
V
EE
pins
I
BB
= 0.4 mA
ECL Clock Outputs (Q0–A19, Q0–Q19)
Output High Voltage
Output Low Voltage
–1.1
–1.9
–1.005
–1.705
–0.7
–1.4
V
V
Supply Current and V
BB
Maximum Quiescent Supply Current without
Output Termination Current
Output Reference Voltage (f
ref
< 1.0 GHz)
(6)
–1.42
84
160
–1.20
mA
V
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
3. Inputs have internal pullup/pulldown resistors which affect the input current.
4. Equivalent to a termination of 50
Ω
to V
TT
.
5. I
CC
calculation: I
CC
= (number of differential output used) x (I
OH
+ I
OL
) + I
EE
I
CC
= (number of differential output used) x (V
OH
– V
TT
)
÷
R
load
+
(V
OL
– V
TT
)
÷
R
load
+
I
EE
.
6. V
BB
can be used to bias unused single-ended inputs up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential signals
should be used with the MC100ES6221.
MC100ES6221
Advanced Clock Drivers Devices
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
