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CA3096E

Description
50 mA, 35 V, 5 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR, MS-001BB
Categorysemiconductor    Discrete semiconductor   
File Size345KB,15 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
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CA3096E Overview

50 mA, 35 V, 5 CHANNEL, NPN AND PNP, Si, SMALL SIGNAL TRANSISTOR, MS-001BB

®
January 2004
UC T
P RO D
TE
D UC T
BSOLE TITUTE PRO
O
S UB S
SIBLE HFA3096
POS
CA3096, CA3096A,
CA3096C
NPN/PNP Transistor Arrays
Description
The CA3096C, CA3096, and CA3096A are general purpose
high voltage silicon transistor arrays. Each array consists of
five independent transistors (two PNP and three NPN types)
on a common substrate, which has a separate connection.
Independent connections for each transistor permit maxi-
mum flexibility in circuit design.
Types CA3096A, CA3096, and CA3096C are identical,
except that the CA3096A specifications include parameter
matching and greater stringency in I
CBO
, I
CEO
, and
V
CE
(SAT). The CA3096C is a relaxed version of the CA3096.
Applications
• Five-Independent Transistors
- Three NPN and
- Two PNP
• Differential Amplifiers
• DC Amplifiers
• Sense Amplifiers
• Level Shifters
• Timers
• Lamp and Relay Drivers
• Thyristor Firing Circuits
• Temperature Compensated Amplifiers
Operational Amplifiers
CA3096, CA3096A, CA3096C
Essential Differences
CHARACTERISTIC
V
(BR)CEO
(V) (Min)
CA3096A
CA3096
CA3096C
Part Number Information
PART NUMBER
(BRAND)
CA3096AE
CA3096AM
(3096A)
CA3096AM96
(3096A)
CA3096CE
CA3096E
CA3096M
(3096)
CA3096M96
(3096)
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC Tape
and Reel
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC Tape
and Reel
PKG.
NO.
E16.3
M16.15
M16.15
E16.3
E16.3
M16.15
M16.15
NPN
PNP
V
(BR)CBO
(V) (Min)
NPN
PNP
h
FE
at 1mA
NPN
PNP
h
FE
at 100µA
PNP
I
CBO
(nA) (Max)
NPN
PNP
35
-40
35
-40
24
-24
45
-40
45
-40
30
-24
150-500
20-200
150-500
20-200
100-670
15-200
40-250
40-250
30-300
Pinout
CA3096, CA3096A, CA3096C
(PDIP, SOIC)
TOP VIEW
1
2
Q
1
3
4
5
6
7
8
Q
3
Q
2
Q
4
Q
5
14
13
12
11
10
9
16
15
SUBSTRATE
40
-40
100
-100
100
-100
I
CEO
(nA) (Max)
NPN
PNP
V
CE SAT
(V) (Max)
NPN
|V
IO
| (mV) (Max)
NPN
PNP
|I
IO
| (µA) (Max)
NPN
PNP
0.6
0.25
-
-
-
-
5
5
-
-
-
-
0.5
0.7
0.7
100
-100
1000
-1000
1000
-1000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
FN595.5

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