PMWD26UN
Dual N-channel
µTrenchMOS
ultra low level FET
Rev. 02 — 19 May 2005
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package
using TrenchMOS technology.
1.2 Features
s
Surface-mounted package
s
Very low threshold voltage
s
Low profile
s
Fast switching
1.3 Applications
s
Portable appliances
s
Battery management
s
PCMCIA cards
s
Load switching
1.4 Quick reference data
s
V
DS
≤
20 V
s
P
tot
≤
3.1 W
s
I
D
≤
7.8 A
s
R
DSon
≤
30 mΩ
2. Pinning information
Table 1:
Pin
1
2, 3
4
5
6, 7
8
Pinning
Description
drain1 (D1)
source1 (S1)
gate1 (G1)
gate2 (G2)
source2 (S2)
drain2 (D2)
1
4
S
1
G
1
S
2
G
2
msd901
Simplified outline
8
5
Symbol
D
1
D
2
SOT530-1 ((TSSOP8)
Philips Semiconductors
PMWD26UN
Dual N-channel
µTrenchMOS
ultra low level FET
3. Ordering information
Table 2:
Ordering information
Package
Name
PMWD26UN
TSSOP8
Description
plastic thin shrink small outline package; 8 leads; body width 4.4 mm
Version
SOT530-1
Type number
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
[1]
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
T
sp
= 25
°C;
V
GS
= 4.5 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 4.5 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
[1]
[1]
[1]
[1]
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
20
20
±10
7.8
4.7
31.3
3.1
+150
+150
2.6
10.3
Unit
V
V
V
A
A
A
W
°C
°C
A
A
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
Source-drain diode
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
Single device conducting.
9397 750 14982
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 May 2005
2 of 12
Philips Semiconductors
PMWD26UN
Dual N-channel
µTrenchMOS
ultra low level FET
120
P
der
(%)
80
03aa17
120
I
der
(%)
80
03aa25
40
40
0
0
50
100
150
T
sp
(
°
C)
200
0
0
50
100
150
T
sp
(
°
C)
200
P
der
P
tot
=
------------------------
×
100
%
P
°
tot
(
25 C
)
V
GS
≥
4.5 V
I
D
I
der
=
--------------------
×
100
%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature
10
2
I
D
(A)
10
Fig 2. Normalized continuous drain current as a
function of solder point temperature
003aaa266
Limit R
DSon
= V
DS
/I
D
t
p
= 10
µ
s
100
µ
s
1 ms
1
DC
10 ms
100 ms
10
-1
10
-2
10
-1
1
10
V
DS
(V)
10
2
T
sp
= 25
°C;
I
DM
is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14982
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 May 2005
3 of 12
Philips Semiconductors
PMWD26UN
Dual N-channel
µTrenchMOS
ultra low level FET
5. Thermal characteristics
Table 4:
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
mounted on a printed-circuit
board; minimum footprint;
vertical in still air
Min
-
-
Typ
-
100
Max
40
-
Unit
K/W
K/W
thermal resistance from junction to solder point
thermal resistance from junction to ambient
Symbol Parameter
10
2
Z
th(j-sp)
(K/W)
003aaa267
δ
= 0.5
0.2
0.1
0.05
0.02
P
δ
=
t
p
T
10
1
single pulse
t
p
T
t
10
-1
10
-4
10
-3
10
-2
10
-1
1
10
t
p
(s)
10
2
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
9397 750 14982
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 May 2005
4 of 12
Philips Semiconductors
PMWD26UN
Dual N-channel
µTrenchMOS
ultra low level FET
6. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol
V
(BR)DSS
Parameter
drain-source breakdown voltage
Conditions
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
I
DSS
gate-source threshold voltage
drain-source leakage current
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
and
10
V
DS
= 20 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 3.5 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 1.8 V; I
D
= 3.5 A;
Figure 7
and
8
V
GS
= 2.5 V; I
D
= 3.5 A;
Figure 7
and
8
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 4 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 4 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V;
V
R
= 20 V
V
DS
= 10 V; R
L
= 1
Ω;
V
GS
= 4.5 V;
R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 16 V; f = 1 MHz;
Figure 11
I
D
= 4 A; V
DS
= 16 V; V
GS
= 4.5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
23.6
2.1
6.7
399
239
14
22
56
33
0.67
45
13
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
-
26
44
34
29
30
51
40
35
mΩ
mΩ
mΩ
mΩ
-
-
-
-
-
-
1
100
100
µA
µA
nA
20
18
0.45
-
-
0.7
-
-
-
V
V
V
Min
Typ
Max
Unit
Static characteristics
1366 -
Source-drain diode
9397 750 14982
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 19 May 2005
5 of 12
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