IDT72275L10PF datasheet, PDF - EEWORLD Datasheet

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IDT72275L10PF: Description32K X 18 OTHER FIFO, 6.5 ns, PQFP64; Categorystorage; File Size227KB，25 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72275L10PF Overview

32K X 18 OTHER FIFO, 6.5 ns, PQFP64

IDT72275L10PF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	6.5 ns
Processing package description	Plastic, TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, low PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
memory width	18
organize	32K × 18
storage density	589824 deg
operating mode	Synchronize
Number of digits	32768 words
Number of digits	32K
cycle	10 ns
Output enable	Yes
Memory IC type	Other first in first out

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CMOS SUPERSYNC FIFO™

32,768 x 18

65,536 x 18

Integrated Device Technology, Inc.

PRELIMINARY

IDT72275

IDT72285

FEATURES:

• Choose among the following memory organizations:

IDT72275

32,768 x 18

IDT72285

65,536 x 18

• Pin-compatible with the IDT72255LA/72265LA SuperSync

FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and

writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the

64-pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

DESCRIPTION:

The IDT72275/72285 are exceptionally deep, high speed,

CMOS First-In-First-Out (FIFO) memories with clocked read

and write controls. These FIFOs offer numerous improve-

ments over previous SuperSync FIFOs, including the following:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency

Select pin (FS) has been removed, thus it is no longer

necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

• The first word data latency period, from the time the first

word is written to an empty FIFO to the time it can be read,

is now fixed and short. (The variable clock cycle counting

FUNCTIONAL BLOCK DIAGRAM

WCLK

-D

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

32,768 x 18

65,536 x 18

FLAG

LOGIC

FWFT/SI

READ POINTER

WRITE POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

RESET

LOGIC

RCLK

-Q

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

4674 drw 01

COMMERCIAL TEMPERATURE RANGE

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

SEPTEMBER 1998

DSC-4674/-

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