GS8322Z72GC-166EV datasheet, PDF

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GS8322Z72GC-166EV: DescriptionSRAM 1.8/2.5V 512K x 72 36M; Categorystorage; File Size419KB，28 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8322Z72GC-166EV Overview

SRAM 1.8/2.5V 512K x 72 36M

GS8322Z72GC-166EV Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	GSI Technology
Product Category	SRAM
RoHS	Details
Memory Size	36 Mbit
Organization	512 k x 72
Access Time	8 ns
Maximum Clock Frequency	166 MHz
Interface Type	Parallel
Supply Voltage - Max	2.7 V
Supply Voltage - Min	1.7 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 125 C
Mounting Style	SMD/SMT
Package / Case	BGA-209
Packaging	Tray
Memory Type	SDR
Type	NBT
Moisture Sensitive	Yes
Factory Pack Quantity	14

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GS8322Z2(C)-xxxV

09 BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 209-Bump BGA package

• RoHS-compliant package available

36Mb Pipelined and Flow Through

Synchronous NBT SRAM

250 MHz–133 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8322Z72-xxxV may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8322Z72-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 209-bump BGA package.

Functional Description

The GS8322Z72-xxxV is a 36Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Parameter Synopsis

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

tCycle

Curr

(x72)

tCycle

Curr

(x72)

-250 -225 -200 -166 -150 -133 Unit

3.0 3.0 3.0 3.5 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

415

6.5

300

385 340 305 285 255 mA

7.0 7.5 8.0 8.5 8.5 ns

280 255 245 230 225 mA

Rev: 1.07 10/2014

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z72GC-166EV Related Products

	GS8322Z72GC-166EV	GS8322Z72GC-150EV	GS8322Z72GC-225EV	GS8322Z72GC-250EV	GS8322Z72GC-133EV
Description	SRAM 1.8/2.5V 512K x 72 36M	SRAM 1.8/2.5V 512K x 72 36M	SRAM 1.8/2.5V 512K x 72 36M	Static random access memory 1.8/2.5V 512K x 72 36M	Static random access memory 1.8/2.5V 512K x 72 36M
Product Category	SRAM	SRAM	SRAM	static random access memory	static random access memory
Interface Type	Parallel	Parallel	Parallel	Parallel	Parallel
Product Attribute	Attribute Value	Attribute Value	Attribute Value	-	-
Manufacturer	GSI Technology	GSI Technology	GSI Technology	-	-
RoHS	Details	Details	Details	-	-
Memory Size	36 Mbit	36 Mbit	36 Mbit	-	-
Organization	512 k x 72	512 k x 72	512 k x 72	-	-
Access Time	8 ns	8.5 ns	7 ns	-	-
Maximum Clock Frequency	166 MHz	150 MHz	225 MHz	-	-
Supply Voltage - Max	2.7 V	2.7 V	2.7 V	-	-
Supply Voltage - Min	1.7 V	1.7 V	1.7 V	-	-
Minimum Operating Temperature	- 40 C	- 40 C	- 40 C	-	-
Maximum Operating Temperature	+ 125 C	+ 125 C	+ 125 C	-	-
Mounting Style	SMD/SMT	SMD/SMT	SMD/SMT	-	-
Package / Case	BGA-209	BGA-209	BGA-209	-	-
Packaging	Tray	Tray	Tray	-	-
Memory Type	SDR	SDR	SDR	-	-
Type	NBT	NBT	NBT	-	-
Moisture Sensitive	Yes	Yes	Yes	-	-
Factory Pack Quantity	14	14	14	-	-

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