M54HC4514
RAD-HARD 4 TO 16 LINE DECODER/LATCH
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 20 ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 4514
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9205-019
DILC-24
FPC-24
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC4514D
M54HC4514K
EM
M54HC4514D1
M54HC4514K1
DESCRIPTION
The M54HC4514 is an high speed CMOS 4 LINE
TO 16 LINE SEGMENT DECODER WITH
LATCHED INPUTS fabricated with silicon gate
C
2
MOS technology.
A binary code stored in the four input latches (A to
D) provides a high level at the selected one of
PIN CONNECTION
sixteen outputs excluding the other fifteen outputs,
when the inhibit input (INHIBIT) is held low. When
the inhibit input (INHIBIT) is held high, all outputs
are kept low level, while the latch function is
available. The data applied to the data inputs are
transferred to the Q outputs of latches when the
strobe input is held high. When the strobe input is
taken low, the information data applied to the data
input at a time is retained at the output of the
latches.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
May 2004
Rev. 1
1/10
M54HC4514
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
1
2, 3, 21, 22
11, 9, 10, 8,
7, 6, 5, 4, 18,
17, 20, 19,
14, 13, 16,
15
23
12
24
SYMBOL
STROBE
A to D
S0 to S15
NAME AND FUNCTION
Strobe Input
Address Inputs
Multiplexer Outputs
(Active HIGH)
INHIBIT
GND
V
CC
Enable Input
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
STROBE
INHIBIT
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X : Don’t Care
SELECT OUTPUT
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
ALL OUTPUTS "L"
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
STROBE = "H"
Refer to truth table
STROBE = "L"
Data at the negative going
transition of strobe shall
be provided on the each
output while strobe is held
low.
2/10
M54HC4514
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 3: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
P
D
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Power Dissipation
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
300
-65 to +150
265
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
3/10
M54HC4514
Table 6: AC Electrical Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
T
A
= 25°C
Min.
Typ.
30
8
7
65
22
19
75
24
20
60
20
17
14
6
6
10
2
1
Max.
75
15
13
175
35
30
175
35
30
175
35
30
75
15
13
50
10
9
5
5
5
Value
-40 to 85°C
Min.
Max.
95
19
16
220
44
37
220
44
37
220
44
37
95
19
16
65
13
11
5
5
5
-55 to 125°C
Min.
Max.
110
25
23
230
56
45
260
56
45
260
56
45
110
26
23
80
20
17
5
5
5
ns
Unit
t
TLH
t
THL
Output Transition
Time
t
PLH
t
PHL
Propagation Delay
Time
(DATA - Sn)
t
PLH
t
PHL
Propagation Delay
Time
(STROBE- Sn.)
t
PLH
t
PHL
Propagation Delay
Time
(INHIBIT - Sn)
t
W(L)
Minimum Pulse
Width
(STROBE)
Minimum Set Up
Time
(DATA)
Minimum Hold
Time
(DATA)
ns
ns
ns
ns
t
s
ns
t
h
ns
Table 7: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
Typ.
5
61
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
5/10
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