PI7C8148A
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support
devices or systems unless a specific written agreement pertaining to such intended use is executed between the
manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury
to the user.
2) A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or
specifications at any time, without notice, in order to improve design or performance and to supply the best
possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry
described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no
representations that circuitry described herein is free from patent infringement or other rights of third parties
which may result from its use. No license is granted by implication or otherwise under any patent, patent
rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
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JUNE 2004 – Revision 1.04
PI7C8148A
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
SIGNAL DEFINITIONS.............................................................................................................................13
1.1
SIGNAL TYPES....................................................................................................................................13
1.2
SIGNALS ..............................................................................................................................................13
1.2.1
PRIMARY BUS INTERFACE SIGNALS
...................................................................................13
1.2.2
SECONDARY BUS INTERFACE SIGNALS
.............................................................................14
1.2.3
CLOCK SIGNALS
........................................................................................................................16
1.2.4
MISCELLANEOUS SIGNALS
....................................................................................................16
1.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
.................................................................17
1.2.6
POWER AND GROUND..............................................................................................................17
1.3
PIN LIST – 160-PIN LFBGA.................................................................................................................18
2
PCI BUS OPERATION...............................................................................................................................19
2.1
TYPES OF TRANSACTIONS ..............................................................................................................19
2.2
SINGLE ADDRESS PHASE.................................................................................................................20
2.3
DEVICE SELECT (DEVSEL#) GENERATION ..................................................................................20
2.4
DATA PHASE.......................................................................................................................................20
2.5
WRITE TRANSACTIONS....................................................................................................................20
2.5.1
MEMORY WRITE TRANSACTIONS.........................................................................................21
2.5.2
MEMORY WRITE AND INVALIDATE
.....................................................................................22
2.5.3
DELAYED WRITE TRANSACTIONS
........................................................................................22
2.5.4
WRITE TRANSACTION BOUNDARIES...................................................................................23
2.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................23
2.5.6
FAST BACK-TO-BACK TRANSACTIONS
................................................................................23
2.6
READ TRANSACTIONS .....................................................................................................................24
2.6.1
PREFETCHABLE READ TRANSACTIONS
.............................................................................24
2.6.2
DYNAMIC PREFETCHING CONTROL....................................................................................24
2.6.3
NON-PREFETCHABLE READ TRANSACTIONS
...................................................................24
2.6.4
READ PREFETCH ADDRESS BOUNDARIES
........................................................................25
2.6.5
DELAYED READ REQUESTS
...................................................................................................25
2.6.6
DELAYED READ COMPLETION WITH TARGET
.................................................................26
2.6.7
DELAYED READ COMPLETION ON INITIATOR BUS.........................................................26
2.6.8
FAST BACK-TO-BACK READ TRANSACTIONS
....................................................................27
2.7
CONFIGURATION TRANSACTIONS................................................................................................27
2.7.1
TYPE 0 ACCESS TO PI7C8148A................................................................................................28
2.7.2
TYPE 1 TO TYPE 0 CONVERSION
...........................................................................................28
2.7.3
TYPE 1 TO TYPE 1 FORWARDING
..........................................................................................29
2.7.4
SPECIAL CYCLES.......................................................................................................................30
2.8
TRANSACTION TERMINATION.......................................................................................................30
2.8.1
MASTER TERMINATION INITIATED BY PI7C8148A
..........................................................31
2.8.2
MASTER ABORT RECEIVED BY PI7C8148A
.........................................................................32
2.8.3
TARGET TERMINATION RECEIVED BY PI7C8148A
...........................................................32
2.8.4
TARGET TERMINATION INITIATED BY PI7C8148A...........................................................34
3
ADDRESS DECODING..............................................................................................................................36
3.1
ADDRESS RANGES ............................................................................................................................36
3.2
I/O ADDRESS DECODING..................................................................................................................36
3.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
.........................................................................37
3.2.2
ISA MODE
....................................................................................................................................37
3.3
MEMORY ADDRESS DECODING .....................................................................................................38
3.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
..................................38
3.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
..........................39
Page 5 of 90
JUNE 2004 – Revision 1.04
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