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SPD08N05L

Description
SIPMOS-R POWER TRANSISTOR
CategoryDiscrete semiconductor    The transistor   
File Size115KB,8 Pages
ManufacturerInfineon
Websitehttp://www.infineon.com/
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SPD08N05L Overview

SIPMOS-R POWER TRANSISTOR

SPD08N05L Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerInfineon
Parts packaging codeTO-252
package instructionPLASTIC, TO-252, 3 PIN
Contacts4
Reach Compliance Code_compli
ECCN codeEAR99
Factory Lead Time1 week
Other featuresLOGIC LEVEL COMPATIBLE
Avalanche Energy Efficiency Rating (Eas)35 mJ
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage55 V
Maximum drain current (Abs) (ID)8.4 A
Maximum drain current (ID)8.4 A
Maximum drain-source on-resistance0.15 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-252
JESD-30 codeR-PSSO-G2
JESD-609 codee0
Number of components1
Number of terminals2
Operating modeENHANCEMENT MODE
Maximum operating temperature175 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)24 W
Maximum pulsed drain current (IDM)34 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
SPD 08N05L
SIPMOS® Power Transistor
Features
N channel
Product Summary
Drain source voltage
Drain-Source on-state resistance
Continuous drain current
V
DS
R
DS(on)
I
D
55
0.1
8.4
V
A
Enhancement mode
Avalanche rated
Logic Level
dv/dt rated
175˚C operating temperature
Type
SPD08N05L
SPU08N05L
Package
P-TO252
P-TO251
Ordering Code
Q67040-S4134
Packaging
Tape and Reel
Pin 1
G
Pin 2
D
Pin 3
S
Q67040-S4182-A2 Tube
MaximumRatings
, at
Tj
= 25 ˚C, unless otherwise specified
Symbol
Parameter
Continuous drain current
Value
8.4
5.9
34
35
2.4
6
Unit
A
I
D
T
C
= 25 ˚C
T
C
= 100 ˚C
Pulsed drain current
I
Dpulse
E
AS
E
AR
dv/dt
T
C
= 25 ˚C
Avalanche energy, single pulse
mJ
I
D
= 8.4 A,
V
DD
= 25 V,
R
GS
= 25
Avalanche energy, periodic limited by
T
jmax
Reverse diode dv/dt
kV/µs
I
S
= 8.4 A,
V
DS
= 40 V, di/dt = 200 A/µs,
T
jmax
= 175 ˚C
Gate source voltage
Power dissipation
V
GS
P
tot
T
j ,
T
stg
±
20
24
-55... +175
55/175/56
V
W
˚C
T
C
= 25 ˚C
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
Data Sheet
1
06.99

SPD08N05L Related Products

SPD08N05L Q67040-S4134 Q67040-S4182-A2 SPU08N05L
Description SIPMOS-R POWER TRANSISTOR SIPMOS-R POWER TRANSISTOR SIPMOS-R POWER TRANSISTOR SIPMOS-R POWER TRANSISTOR

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