MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CLB120
FLAT-BASE TYPE
INSULATED PACKAGE
PM50CLB120
FEATURE
a) Adopting new 5th generation IGBT (CSTBT) chip, which
performance is improved by 1µm fine rule process.
For example, typical V
ce
(sat)=1.9V @Tj=125°C
b) I adopt the over-temperature conservation by Tj detection of
CSTBT chip, and error output is possible from all each con-
servation upper and lower arm of IPM.
c) New small package
Reduce the package size by 32%, thickness by 22% from
S-DASH series.
• 3φ 50A, 1200V Current-sense IGBT type inverter
• Monolithic gate drive & protection logic
• Detection, protection & status indication circuits for, short-
circuit, over-temperature & under-voltage (P-Fo available
from upper arm devices)
• Acoustic noise-less 5.5kW/7.5kW class inverter application
APPLICATION
General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES
120
7
19.75
106
66.5
16
2
2
16
2
16
2
Dimensions in mm
4-
φ
2.5
3.25
4 4
17.5
25.75
50.75
17.5
1
5
9
13
19
25
2.5
71.5
B
U
V
W
55
5
N
P
Terminal code
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
VUPC
UFO
UP
VUP1
VVPC
VFO
VP
VVP1
VWPC
WFO
11.
12.
13.
14.
15.
16.
17.
18.
19.
WP
VWP1
VNC
VN1
NC
UN
VN
WN
Fo
2 -
φ
7.5
4 4
5.5
4 4
2.5
19.5
22
7.75
23
4 4
23
4 4
23
4 4
98.25
1.5
1
2-φ2.5
1
0.5
2
10.5
27.5
17
16
8.5
Oct. 2003
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CLB120
FLAT-BASE TYPE
INSULATED PACKAGE
INTERNAL FUNCTIONS BLOCK DIAGRAM
NC Fo
V
NC
W
N
V
N1
V
N
U
N
W
P
V
WP1
V
WPC
WF
O
V
P
V
VPC
V
VP1
VF
O
U
P
V
UPC
V
UP1
UF
O
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd In
Fo Vcc
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
Gnd
Si Out
OT
NC
N
W
V
U
P
MAXIMUM RATINGS
(Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CES
±I
C
±I
CP
P
C
T
j
Parameter
Collector-Emitter Voltage
Collector Current
Collector Current (Peak)
Collector Dissipation
Junction Temperature
Condition
V
D
= 15V, V
CIN
= 15V
T
C
= 25°C
T
C
= 25°C
T
C
= 25°C
Ratings
1200
50
100
369
–20 ~ +150
Unit
V
A
A
W
°C
(Note-2)
CONTROL PART
Symbol
V
D
V
CIN
V
FO
I
FO
Parameter
Supply Voltage
Input Voltage
Fault Output Supply Voltage
Fault Output Current
Condition
Applied between : V
UP1
-V
UPC
V
VP1
-V
VPC
, V
WP1
-V
WPC
, V
N1
-V
NC
Applied between : U
P
-V
UPC
, V
P
-V
VPC
W
P
-V
WPC
, U
N
• V
N
• W
N
-V
NC
Applied between : U
FO
-V
UPC
, V
FO
-V
VPC
, W
FO
-V
WPC
F
O
-V
NC
Sink current at U
FO
, V
FO
, W
FO
, F
O
terminals
Ratings
20
20
20
20
Unit
V
V
V
mA
Oct. 2003
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CLB120
FLAT-BASE TYPE
INSULATED PACKAGE
TOTAL SYSTEM
Parameter
Supply Voltage Protected by
V
CC(PROT)
SC
V
CC(surge)
Supply Voltage (Surge)
Module Case Operating
T
C
Temperature
Storage Temperature
T
stg
V
iso
Isolation Voltage
Symbol
Condition
V
D
= 13.5 ~ 16.5V, Inverter Part,
T
j
= +125°C Start
Applied between : P-N, Surge value
(Note-2)
Ratings
800
1000
–20 ~ +100
–40 ~ +125
2500
Unit
V
V
°C
°C
V
rms
60Hz, Sinusoidal, Charged part to Base, AC 1 min.
THERMAL RESISTANCES
Symbol
R
th(j-c)Q
R
th(j-c)F
R
th(j-c)Q
R
th(j-c)F
R
th(c-f)
Parameter
Junction to case Thermal
Resistances
Condition
Inverter IGBT (per 1 element)
Inverter FWDi (per 1 element)
Inverter IGBT (per 1 element)
Inverter FWDi (per 1 element)
Case to fin, (per 1 module)
Thermal grease applied
(Note-1)
(Note-1)
(Note-2)
(Note-2)
Min.
—
—
—
—
—
Limits
Typ.
—
—
—
—
—
Max.
0.26
0.39
0.34
0.51
0.038
Unit
°C/W
Contact Thermal Resistance
(Note-1) T
C
measurement point is just under the chips (Bottom view).
If you use this value, R
th(f-a)
should be measured just under the chips.
(Note-2) T
C
measurement point is as shown below (Top view).
Table1 : T
C
measurement point of just under the chips.
arm
axis
X
Y
UP
IGBT FWDi
28.3
28.4
–7.7
1.5
VP
IGBT FWDi
65.0
64.9
–7.7
1.5
WP
IGBT FWDi
87.0
86.9
–7.7
1.5
UN
IGBT FWDi
39.3
39.2
5.7
–3.5
V
W
(Unit : mm)
VN
IGBT FWDi
54.0
54.1
5.7
–3.5
B
U
WN
IGBT FWDi
76.0
76.1
5.7
–3.5
Bottom view
Top view
T
C
(Base plate)
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
V
CE(sat)
V
EC
t
on
t
rr
t
c(on)
t
off
t
c(off)
I
CES
Parameter
Collector-Emitter
Saturation Voltage
FWDi Forward Voltage
Condition
V
D
= 15V, I
C
= 50A
V
CIN
= 0V, Pulsed
(Fig. 1)
–I
C
= 50A, V
D
= 15V, V
CIN
= 15V
V
D
= 15V, V
CIN
= 0V↔15V
V
CC
= 600V, I
C
= 50A
T
j
= 125°C
Inductive Load
V
CE
= V
CES
, V
CIN
= 15V
(Fig. 5)
T
j
= 25°C
T
j
= 125°C
(Fig. 2)
Min.
—
—
—
0.5
—
—
—
—
—
—
Limits
Typ.
1.8
1.9
2.5
1.0
0.5
0.4
2.0
0.7
—
—
Max.
2.3
2.4
3.5
2.5
0.8
1.0
3.0
1.2
1
10
Unit
V
V
N
P
Switching Time
µs
(Fig. 3,4)
T
j
= 25°C
T
j
= 125°C
Collector-Emitter
Cutoff Current
mA
Oct. 2003
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CLB120
FLAT-BASE TYPE
INSULATED PACKAGE
CONTROL PART
Symbol
I
D
V
th(ON)
V
th(OFF)
SC
t
off(SC)
OT
OT
r
UV
UV
r
I
FO(H)
I
FO(L)
t
FO
Parameter
Circuit Current
Input ON Threshold Voltage
Input OFF Threshold Voltage
Short Circuit Trip Level
Short Circuit Current Delay
Time
Over Temperature Protection
Supply Circuit Under-Voltage
Protection
Fault Output Current
Minimum Fault Output Pulse
Width
V
D
= 15V, V
CIN
= 15V
Condition
V
N1
-V
NC
V
XP1
-V
XPC
Min.
—
—
1.2
1.7
100
—
135
—
11.5
—
—
—
1.0
Limits
Typ.
15
5
1.5
2.0
—
0.2
145
125
12.0
12.5
—
10
1.8
Max.
25
10
1.8
2.3
—
—
155
—
12.5
—
0.01
15
—
Unit
mA
V
A
µs
°C
V
mA
ms
Applied between : U
P
-V
UPC
, V
P
-V
VPC
, W
P
-V
WPC
U
N
• V
N
• W
N
-V
NC
(Fig. 3,6)
–20
≤
T
j
≤
125°C, V
D
= 15V
V
D
= 15V
Detect T
j
of IGBT chip
–20
≤
T
j
≤
125°C
V
D
= 15V, V
CIN
= 15V
V
D
= 15V
(Fig. 3,6)
Trip level
Reset level
Trip level
Reset level
(Note-3)
(Note-3)
(Note-3) Fault output is given only when the internal SC, OT & UV protections schemes of either upper or lower arm device operate to
protect it.
MECHANICAL RATINGS AND CHARACTERISTICS
Symbol
—
—
Parameter
Mounting torque
Weight
Mounting part
—
Condition
screw : M5
Min.
2.5
—
Limits
Typ.
3.0
340
Max.
3.5
—
Unit
N•m
g
RECOMMENDED CONDITIONS FOR USE
Symbol
V
CC
V
D
V
CIN(ON)
V
CIN(OFF)
f
PWM
t
dead
Parameter
Supply Voltage
Control Supply Voltage
Input ON Voltage
Input OFF Voltage
PWM Input Frequency
Arm Shoot-through
Blocking Time
Condition
Applied across P-N terminals
Applied between : V
UP1
-V
UPC
, V
VP1
-V
VPC
V
WP1
-V
WPC
, V
N1
-V
NC
(Note-4)
Applied between : U
P
-V
UPC
, V
P
-V
VPC
, W
P
-V
WPC
U
N
• V
N
• W
N
-V
NC
Using Application Circuit of Fig. 8
For IPM’s each input signals
(Fig. 7)
Recommended value
≤
800
15.0
±
1.5
≤
0.8
≥
9.0
≤
20
≥
2.5
Unit
V
V
V
kHz
µs
(Note-4) With ripple satisfying the following conditions dv/dt swing
≤ ±5V/µs,
Variation
≤
2V peak to peak
Oct. 2003
MITSUBISHI <INTELLIGENT POWER MODULES>
PM50CLB120
FLAT-BASE TYPE
INSULATED PACKAGE
PRECAUTIONS FOR TESTING
1. Before appling any control supply voltage (V
D
), the input terminals should be pulled up by resistores, etc. to their corre-
sponding supply voltage and each input signal should be kept off state.
After this, the specified ON and OFF level setting for each input signal should be done.
2. When performing “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not be al-
lowed to rise above V
CES
rating of the device.
(These test should not be done by using a curve tracer or its equivalent.)
P, (U,V,W)
IN
Fo
IN
Fo
P, (U,V,W)
V
CIN
(0V)
V
Ic
V
CIN
(15V)
V
–
Ic
V
D
(all)
U,V,W, (N)
V
D
(all)
U,V,W, (N)
Fig. 1 V
CE(sat)
Test
Fig. 2 V
EC
Test
a) Lower Arm Switching
P
V
CIN
(15V)
V
CIN
Signal input
(Upper Arm)
Signal input
(Lower Arm)
Fo
Fo
U,V,W
trr
Irr
C
S
V
CE
Ic
90%
Vcc
90%
N
b) Upper Arm Switching
V
CIN
Signal input
(Upper Arm)
Signal input
(Lower Arm)
V
D
(all)
P
Ic
10%
10%
tc (on)
10%
tc (off)
10%
Fo
U,V,W
V
CIN
C
S
Vcc
td (on)
tr
td (off)
tf
V
CIN
(15V)
Fo
(ton= td (on) + tr)
N
(toff= td (off) + tf)
V
D
(all)
Ic
Fig. 3 Switching time and SC test circuit
Fig. 4 Switching time test waveform
V
CIN
Short Circuit Current
P, (U,V,W)
A
IN
Fo
Constant Current
SC
Pulse
V
CE
V
CIN
(15V)
Ic
V
D
(all)
U,V,W, (N)
Fo
toff(SC)
Fig. 5 I
CES
Test
Fig. 6 SC test waveform
IPM’ input signal V
CIN
(Upper Arm)
0V
IPM’ input signal V
CIN
(Lower Arm)
1.5V
2V
1.5V
t
0V
2V
1.5V
2V
t
t
dead
t
dead
t
dead
1.5V: Input on threshold voltage Vth(on) typical value, 2V: Input off threshold voltage Vth(off) typical value
Fig. 7 Dead time measurement point example
Oct. 2003
MCU
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