(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
FEATURES
•
•
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for
all frequencies
.
Low phase noise output (@ 1MHz frequency
offset
∗
-140dBc/Hz for 311.04MHz,
∗
-131dBC/Hz for 622.08MHz
19MHz-40MHz crystal input.
38MHz-640MHz output.
Selectable PECL, LVDS, or CMOS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
DIE CONFIGURATION
65 mil
OUTSEL0
v
OUTSEL1^
VDDOSC
VDDANA
VDDANA
VDDDIG
SEL0^
SEL1^
(1550,1475)
17
16
•
•
•
•
•
•
•
•
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
SEL2
62 mil
26
Die ID:
2222-22A
27
15
28
14
13
DNC
29
12
11
OE_CTRL
30
DESCRIPTION
The PL580-30 is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and PECL, LVDS, or CMOS outputs, covering a
wide frequency output range up to 640MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
The PL580-30 is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, XDSL, etc.
VCON
31
1
C502A
10
9
2
3
4
5
6
7
8
GNDOSC
GNDANA
Y
X
(0,0)
Note1: ^ Denotes internal pull up resistor.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
VCON
VARICAP
VCO
Divider
Charge
Pump
+
Loop
Filter
XIN
XOUT
XTAL
OSC
Phase
Detector
VCO
(F
XiN
x16)
Output
Divider
(1,2,4,8)
GNDBUF
DNC
LM
DNC
LP
GNDDIG
QBAR
Q
Perform ance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/30/05 Page 1
(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
OUTSEL0
(Pad #25)
0
0
1
1
v
OUTSEL1^
(Pad #18)
0
1
0
1
Selected Output
LVDS
PECL (Default)
High Drive CMOS
Standard Drive CMOS
Note: For bonding convenience, ‘OUTSEL0’ incorporates an internal pull down resistor while ‘OUTSEL1’ incorporates an internal pull up resistor.
OUTPUT SELECTION AND ENABLE
OE_SEL^
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”,
Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
FREQUENCY SELECTION TABLE
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Selected Multiplier/Output Frequency
VCO Max*
VCO Min*
Reserved
Reserved
Fin x 2
Fin x 8
Fin x 16
Fin x 4
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/30/05 Page 2
(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
GNDOSC
GNDANA
LP
LM
DNC
DNC
GNDDIG
GNDBUF
OE_SELECT
LVDS
PECL
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
GNDBUF
OUTSEL1
SEL1
SEL0
VDDDIG
VDDANA
VDDANA
VDDOSC
OUTSEL0B
XIN
XOUT
SEL2
DNC
OE_CTRL
VCON
X (µm)
248
361
473
587
702
874
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
659
559
459
358
194
109
109
109
109
109
109
Y (µm)
109
109
109
109
109
109
109
109
125
259
476
616
716
871
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
646
397
181
Used to select multiplication factor. Incorporates internal pull up.
3.3V power supply, Digital circuitry.
3.3V power supply, Analog circuitry.
3.3V power supply, Analog circuitry.
3.3V power supply, Oscillator circuitry.
Used to select CMOS, PECL or LVDS output type. Incorporates
internal pull down.
Crystal input. See crystal specification for details.
Crystal output. See crystal specification for details.
Used to select multiplication factor. Incorporates internal pull up.
Do Not Connect
Used to enable/disable the output(s). See Output Selection and
Enable table.
Voltage Control Input. 0V to 3.3V.
Ground, Oscillator circuitry.
Ground, Analog circuitry.
Performance/Frequency tuning Inductor.
Performance/Frequency tuning Inductor.
Do No Connect.
Do No Connect.
Ground, Digital circuitry.
Ground, buffer circuitry.
Used to select between PECL or CMOS logic states for OE.
Incorporates internal pull up.
LVDS Output.
PECL Output.
3.3V power supply, Buffer circuitry.
3.3V power supply, Buffer circuitry.
Complementary PECL Output.
Complementary LVDS Output.
Single ended CMOS output.
Ground, buffer circuitry.
Used to select CMOS, PECL or LVDS output type. Incorporates
internal pull up.
Description
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/30/05 Page 3
(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values for your application. In addition, the chart below could be used as a reference for quick inductor value
selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning
Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance
enhancement of your custom board design, please follow the following instruction:
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/30/05 Page 4
(Preliminary)
PL580-30
38MHz-640MHz Low Phase Noise VCXO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
at VCON = 0V
at VCON = 1.65V
at VCON = 3.3V
AT cut
AT cut
MIN.
19
TYP.
17.7
9.5
5.4
MAX.
40
UNITS
MHz
pF
250
30
-
Ω
Note:
Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package
parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note,
that frequency pulling and oscillator gain may decrease.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 19 – 40MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
500
±200
150
10
60
25
0V
≤
VCON
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/30/05 Page 5
Analog electronics
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