EEWORLDEEWORLDEEWORLD

Part Number

Search

598ACA000653DGR

Description
Programmable Oscillators Any Frequency I2C Programmable XO
CategoryPassive components   
File Size515KB,28 Pages
ManufacturerSilicon Laboratories
Download Datasheet Parametric View All

598ACA000653DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
598ACA000653DGR - - View Buy Now

598ACA000653DGR Overview

Programmable Oscillators Any Frequency I2C Programmable XO

598ACA000653DGR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryProgrammable Oscillators
PackagingBox
Si 5 9 8 / S i 5 9 9
10–810 M H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Features
I
2
C programmable output
frequencies from 10 to 810 MHz
0.5 ps RMS phase jitter
Superior power supply rejection:
0.3–0.4 ps additive jitter
Available LVPECL, CMOS, LVDS,
and CML outputs
1.8, 2.5, or 3.3 V supply
Pin- and register-compatible with
Si570/571
Programmable with 28 parts per
trillion frequency resolution
Integrated crystal provides stability
and low phase noise
Frequency changes up to
±3500 ppm are glitchless
–40 to 85 °C operation
Industry-standard 5x7 mm package
Si5602
Applications
Ordering Information:
SONET / SDH / xDSL
Ethernet / Fibre Channel
3G SDI / HD SDI
Multi-rate PLLs
Multi-rate reference clocks
Frequency margining
Digital PLLs
CPU / FPGA FIFO control
Adaptive synchronization
Agile RF local oscillators
See page 22.
Pin Assignments:
See page 21.
(Top View)
SDA
7
NC
1
2
3
8
SCL
6
5
4
V
DD
Description
The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®
circuitry to provide a low-jitter clock at any frequency. They are user-
programmable to any output frequency from 10 to 810 MHz with 28 parts per
trillion (PPT) resolution. The device is programmed via a 2-pin I
2
C compatible
serial interface. The wide frequency range and ultra-fine programming resolution
make these devices ideal for applications that require in-circuit dynamic frequency
adjustments or multi-rate operation with non-integer related rates. Using an
integrated crystal, these devices provide stable low jitter frequency synthesis and
replace multiple XOs, clock generators, and DAC controlled VCXOs.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
OE
Power Supply Filtering
Si598
SDA
Fixed
Frequency
Oscillator
Any Frequency
DSPLL®
10 to 810 MHz
Clock Synthesis
CLK+
CLK–
7
V
C
1
2
3
8
SCL
6
5
4
V
DD
Vc
(Si599)
OE
CLK–
CLK+
ADC
I2C Interface
GND
SDA
SCL
GND
Si599
Rev. 1.0 11/11
Copyright © 2011 by Silicon Laboratories
Si598/Si599
Show the process of WEBENCH design + high-pass filter design
[i=s]This post was last edited by Yitanqingshui on 2014-8-3 21:31[/i] This design uses webench to design a high-pass filter, and I can fully feel its power and convenience in use. I have used many fil...
一潭清水 Analogue and Mixed Signal
[Rawpixel RVB2601 development board trial experience] Breathing light and red and blue warning light
## Preface The reviewer said that I wrote it too simply, but in fact, I was scared by CDK. This article may be just to make up the numbers, but it can help beginners. # Breathing light Let me briefly ...
韵湖葱白 XuanTie RISC-V Activity Zone
[Ask] Has anyone ported the Bluetooth protocol stack to uCOS?
The situation is this: I am still a student, a rookie, and I want to learn embedded knowledge by making some small things.I want to port the Bluetooth protocol stack to uCOS and connect a Bluetooth mo...
lwb01 Real-time operating system RTOS
Situational Assessment of Automotive Bus Protocols
This article compares the characteristics of several existing mainstream automotive bus systems in detail. These comparisons will help define the next generation of high-security, high-fault-tolerance...
frozenviolet Automotive Electronics
Germany has the strictest enforcement of REACH and violators face huge fines or even imprisonment
Germany has the strictest REACH enforcement, and violations face huge fines or even imprisonment. The basic principle required by the EU REACH regulations - "no data, no market" is enough to stimulate...
keiyi Embedded System
Using Verilog_HDL language to realize the conversion of parallel-to-serial and serial-to-parallel interfaces
[i=s]This post was last edited by paulhyde on 2014-9-15 03:22[/i] Use Verilog_HDL language to implement parallel-to-serial and serial-to-parallel interface conversion....
fpga126 Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2668  296  386  2243  1632  54  6  8  46  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号