Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
FEATURES
•
•
•
•
•
•
Input: 65-130MHz 3
rd
Overtone or fundamental
Crystal
Output frequency: Up to 130MHz
Selectable /2, /4, /8 output dividers with 60KΩ
pull up resistor on the selector pins
Available output: PECL
Supports 2.5V or 3.3V-Power Supply
Available in die form
DIE CONFIGURATION
57.5 mil
GNDOSC
18
VDDOSC
VDDANA
VDDBUF
^SEL0
17
^ SEL1
16
(1460,1435)
15
14
13
12
OECTRL
XIN
56.5 mil
19
OESEL (pull down)
VDDBUF
VDDBUF
Q
Q
GNDBUF
20
10
9
11
XOUT
21
8
DESCRIPTION
PL623-38 is an XO IC specifically designed to work
with high frequency 3
rd
overtone or fundamental
crystals from 65MHz to 135MHz. It requires an
external resistor for the 3
rd
overtone selection. Its
design was optimized to tolerate higher limits of
inter-electrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It is ideal for XO applications requiring
PECL output levels at high frequencies.
Y
X
Die ID: C560A-FFFF-FP
OECTRL
22
1
2
3
4
5
6
7
(0,0)
GNDOSC
GNDANA
GNDASHIELD
Note: ‘^’ Denotes 60kΩ pull-up resistor
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
57.5 x 56.5 mil
GND
80 micron x 80 micron
10 mil
GNDOSC
GNDBSHIELD
GNDBUF
BLOCK DIAGRAM
OECTRL
Q
XIN
3
rd
OT
Resistor
OE SELECTION
Pad #12
OESEL
1
Pad #22
OECTRL
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Oscillator
Amplifier
Q
PL623-38
XOUT
0
(default)
Pad #12: Bond to VDD to set to “1”
Pad #22: Logical states defined by PECL levels
OUTPUT DIVIDER SELECTOR LOGIC
SEL 0
0
1
0
1
SEL1
0
0
1
1
Output
No Divider
Divide by 2
Divide by 4
Divide by 8
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
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Rev 05/03/05 Page 1
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
DIE PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
GNDOSC
GNDOSC
GNDANA
GNDSHIELD
GNDSHIELD
GNDBUF
GNDBUF
Q
QBAR
VDDBUF
VDDBUF
OESEL
VDDBUF
VDDANA
VDDOSC
SEL1
SEL0
GNDOSC
OECTRL
XIN
X (µm)
329.6
498.3
696.2
825.0
973.6
1150.0
1183.6
1183.6
1183.6
1182.4
1252.4
1252.4
1058.5
864.5
624.0
467.1
271.1
109.4
108.9
109.0
Y (µm)
110.1
110.0
110.0
110.0
110.0
109.1
302.2
452.3
613.5
745.9
903.6
1081.3
1221.6
1221.6
1222.7
1222.6
1222.6
1222.9
1062.1
865.8
Pad Description
GND connection for oscillator circuitry.
GND connection for oscillator circuitry.
GND connection for analog circuitry.
GND shielding connection.
GND shielding connection.
GND connection for output buffer circuitry.
GND connection for output buffer circuitry.
PECL output.
Complementary PECL output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
This is the selector input to choose the OE control logic to be
applied, as presented on the OE SELECTION TABLE on page ‘1’.
VDD connection for output buffer circuitry.
VDDBUF should be separately decoupled from other VDDs
whenever possible.
VDD connection for analog circuitry. VDDANA should be
separately decoupled from other VDDs whenever possible.
VDD connection for oscillator circuitry. VDDOSC should be
separately decoupled from other VDDs whenever possible.
Output Divider Selector pin as presented on the DIVIDER
SELECTOR TABLE on page ‘1’.
Output Divider Selector pin as presented on the DIVIDER
SELECTOR TABLE on page ‘1’.
GND connection for oscillator circuitry.
Output Enable input pad. See OE SELECTION TABLE on page 1.
Crystal connector pad. This pad is the input of the crystal
oscillator circuitry. The crystal should be mounted as close to the
IC as possible, with minimum parasitic capacitance.
Crystal connector pad. This pad is the input of the crystal
oscillator circuitry. The crystal should be mounted as close to the
IC as possible, with minimum parasitic capacitance.
Output Enable input pad. See OE SELECTION TABLE on page 1.
21
22
XOUT
OECTRL
108.6
108.6
358.4
146.5
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 05/03/05 Page 2
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
EXTERNAL COMPONENT VALUES – 3
RD
OVERTONE RESISTOR SELECTIONS
This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest “E12”
resistor values versus frequency for PL623-38.
Frequency
(MHz)
65
67.5
70
75
77.5
80
82.5
85
87.5
90
92.5
95
97.5
R3OT
(Ω)
2,162
2,082
2,008
1,875
1,815
1,758
1,705
1,654
1,607
1,563
1,520
1,480
1,442
E12 Pick
KΩ
2.2
2.2
2.2
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.5
1.5
1.5
Frequency
(MHz)
100
102.5
105
107.5
110
112.5
115
117.5
120
122.5
125
127.5
130
R3OT
(Ω)
1,406
1,372
1,339
1,308
1,278
1,250
1,223
1,197
1,172
1,148
1,125
1,103
1,082
E12 Pick
KΩ
1.5
1.5
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.0
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Input Static Discharge Voltage Protection
SYMBOL
V
DD
V
I
V
O
T
S
T
A
MIN.
V
SS
-0.5
V
SS
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
+85
2
UNITS
V
V
V
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 05/03/05 Page 3
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
2. Crystal Specifications
Name
Parallel Resonant mode
Load capacitance (capacitance on
built-in on die seen by crystal)
Inter-electrode capacitance
Equivalent Series Resistance
Oscillation Frequency
C
L
C
0
ESR
3
rd
Overtone
65
Symbol
Conditions
3
rd
Overtone
Die only, no bond wire,
no package
5
4
35
130
Min.
Max.
Units
N/A
pF
pF
Ω
MHz
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBO
L
I
DD
V
DD
CONDITIONS
PECL
MIN.
TYP.
MAX.
85/55
UNITS
mA
V
%
mA
2.25
@ Vdd – 1.3V (PECL)
45
50
±50
3.63
55
4. Jitter Specifications
PARAMETERS
Period jitter RMS at 106.25MHz
Period jitter peak-to-peak at 106.25MHz
Integrated jitter RMS at 106.25MHz
*Measured on Agilent E5500.
CONDITIONS
With capacitive decoupling
between VDD and GND.
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.0
17.0
0.3*
MAX.
UNITS
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise vs. carrier
with fund. crystal.
FREQUENCY
106.25MHz
@10Hz
-55
@100Hz
-90
@1kHz
-110
@10kHz
-135
@100kHz
-145
UNITS
dBc/Hz
*: Note: Phase noise to be measured. Based on P520-20 product (fundamental 155MHz VCXO).
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 05/03/05 Page 4
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
8. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
V
DD
– 1.620
MAX.
UNITS
V
V
9. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.2
0.2
MAX.
0.4
0.4
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 05/03/05 Page 5
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