The PLL601-12 is a highly flexible XO with select-
able multipliers and two CMOS outputs (one of which
can be selected to be REF_CLK). Thanks to Phase-
Link’s advanced Phase Locked Loop technology, it
allows a wide choice of selectable multipliers that
permits the user to achieve useful frequencies from
standard low cost crystals. It accepts fundamental
parallel resonant mode crystals from 13 to 31MHz,
and is ideal to generate 156.25MHz from a standard
25MHz crystal.
^: Internal pull-up.
BLOCK DIAGRAM
[S3,S0]
REF_SEL
XOUT
XIN
Oscillator
Amplifier
PLL
(Phase
Locked
Loop)
CLK2/REF_CLK
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
FREQUENCY SELECTION TABLE
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
19
15
14
13
14
14
14
15
15
16
16
16
14
13
36
28
26
25
27
26
27
28
28
31
31
31
26
25
Xtal
Min
Xtal
Max
Reserved
Reserved
X 4.25
X 11
X 12
X 12.5
X 5.75
X3
X 11.5
X 5.5
X 2.75
X5
X 2.5
X 10
X6
X 6.25
Multiplier
Note:
Internal pull-ups default S3, S2, S1, and S0 to ‘1’ when not connected
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
S3
S2
DRIVE_SEL
GND
CLK1
CLK2/REF_CLK
REF_SEL
S1
S0
Pin #
1,11
2
3
4
5
6
7,8
9
10
12
13
14
Type
P
I
I
I
I
I
P
O
O
I
I
I
Power Supply.
Crystal input.
Crystal output.
Multiplier selector pins. These pins have an internal pull-up that will de-
fault SEL to ‘1’ when not connected to GND.
Selector pin. If DRIVE_SEL is ‘0’, outputs are at high drive. If ‘1’ or not
connected, outputs are standard drive (internal pull-up).
Ground.
CLK1 output is the output of the reference frequency (crystal) after multi-
plication through the Phase Locked Loop.
CLK2 or REF_CLK output (depending on REF_SEL). CLK2 is in phase and
at the same frequency as CLK1. REF_CLK provides the same output as
the crystal reference.
Selector pin. This pin if set to ‘0’ selects REF_CLK on pin 10. If not con-
nected, it defaults to ‘1’ (pin 10 = CLK2). Internal pull-up.
Multiplier selector pins. These pins have an internal pull-up that will de-
fault SEL to ‘1’ when not connected to GND.
Description
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 2
PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
(see Selection Table)
At VCON = 1.65V
AT cut
MIN.
13
TYP.
MAX.
31
UNITS
MHz
pF
Ω
16
30
3. General Electrical Specifications
PARAMETERS
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Short Circuit Current
SYMBOL
I
DD
V
DD
15 pF
load
CONDITIONS
Fout<30MHz
30MHz<Fout<100MHz
Fout >100MHz
MIN.
TYP.
MAX.
15
30
40
3.63
UNITS
mA
V
mA
2.97
±50
4. AC Electrical Specifications
PARAMETERS
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
SYMBOL
CONDITIONS
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
2.0V ~ 0.8V with 10 pF load
3.0V ~ 0.3V with 15pF load
Measured @ 1.4V
MIN.
TYP.
3.7
3.7
50
MAX.
1.5
5
1.5
5
55
UNITS
ns
45
%
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 3
PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
5. Jitter Specifications
PARAMETERS
Max. Absolute Jitter, peak-to-peak
Max. Jitter, cycle to cycle
Phase Noise, relative to carrier, 125Mhz(x5)
Phase Noise, relative to carrier, 125Mhz(x5)
Phase Noise, relative to carrier, 125Mhz(x5)
Phase Noise, relative to carrier, 125Mhz(x5)
CONDITIONS
Short term
100 Hz offset
1kHz offset
10kHz offset
100kHz offset
MIN.
TYP.
60
105
125
130
125
MAX.
100
60
UNITS
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 4
PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
PACKAGE INFORMATION
14 PIN Narrow SOIC ( mm )
SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.35
0.10
0.33
0.19
8.58
3.85
5.80
0.40
1.27 BSC
Max.
1.75
0.25
0.51
0.25
8.69
3.97
6.20
1.27
A1
B
C
L
e
A
D
E
H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL601-12 S C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
S=SOIC
Order Number
PLL601-12SC
PLL601-12SC-R
Marking
P601-12SC
P601-12SC
Package Option
16-Pin SOIC (Tube)
16-Pin SOIC (Tape & Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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