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PLL602-10DC

Description
96MHz ?400MHz Low Phase Noise XO (for 12 ?25MHz Crystals)
File Size112KB,7 Pages
ManufacturerPLL (PhaseLink Corporation)
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PLL602-10DC Overview

96MHz ?400MHz Low Phase Noise XO (for 12 ?25MHz Crystals)

Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
Low phase noise output for the 96MHz to
400MHz range (-134 dBc at 10kHz offset).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
Output Enable selector.
3.3V operation.
Available in DIE (65 mil x 62 mil).
DIE CONFIGURATION
65 mil
(1550,1475)
19
18
17
16
25
26
24
23
22
21
20
27
15
28
14
62 mil
13
29
12
11
30
DESCRIPTIONS
31
10
9
1
2
3
4
5
6
7
8
The PLL602-10 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
Die, with CMOS, LVDS and PECL output, for 96MHz
to 400MHz output range, using a low frequency
crystal.
The same die can be used as a XO with output
frequencies ranging from F
XIN
x 8 to F
XIN
x 16 thanks
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL602-10 ideal for a wide range of applications.
Y
X
(0,0)
MULTIPLIER SELECTION
Pad #19
MULTIPLIER
OUTPUT RANGE
0
1
F
XIN
x 16
F
XIN
x 8
192 – 400 MHz
96 – 200 MHz
Note:
Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
State
Tri-state
Output enabled
OE (Pad #30)
0
1 (Default)
BLOCK DIAGRAM
VCO
Divider
SELECT
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
OE
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1

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