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PLL650-10

Description
Network LAN Clock for Gigabit Ethernet
File Size224KB,5 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Compare View All

PLL650-10 Overview

Network LAN Clock for Gigabit Ethernet

PRELIMINARY
PLL650-10
Network LAN Clock for Gigabit Ethernet
FEATURES
PIN CONFIGURATION
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
Two outputs fixed at 125MHz..
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 8-Pin 150mil SOIC
.
XIN
XOUT
GND
125MHz
1
2
3
4
8
7
6
5
VDD
GND
VDD
125MHz
P LL 650-10
DESCRIPTIONS
The PLL 650-10 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25MHz crystal, and produces multiple output
clocks for networking chips, and ASICs.
BLOCK DIAGRAM
125MHz
XIN
XO UT
XTAL
OS C
C ontrol
Logic
125MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/10/02 Page 1

PLL650-10 Related Products

PLL650-10 PLL650-10SC PLL650-10SI PLL650-10SM
Description Network LAN Clock for Gigabit Ethernet Network LAN Clock for Gigabit Ethernet Network LAN Clock for Gigabit Ethernet Network LAN Clock for Gigabit Ethernet

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Index Files: 2574  1671  131  1635  162  52  34  3  33  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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