Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
FEATURES
•
•
•
•
•
•
•
•
•
•
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable oscillator “on” or “off” ( Sleep Mode )
feature in output disable mode
Ultra Low current consumption ( <2mA, <1.5mA
at 27MHz, 3.3V respectively for PLL600-27 and
PLL600-37)
Ultra Low disable mode current (<2uA when
disabled with osc. off)
10 to 52MHz fundamental or 3
rd
OT crystal input.
12mA drive capability at TTL output.
Low jitter (RMS): 2.5ps period jitter.
1.8V, 2.5V and 3.3V DC operation.
Available in 8 pin SOIC, 6 pin SOT or DIE.
PIN ASSIGNMENT (PACKAGE)
8 pin SOIC
XIN/FIN
N/C
GND
OSCSEL^
1
2
3
4
8
7
6
5
XOUT
OE^
VDD
CLK
^ : denotes internal pull-up
6 pin SOT
CLK
GND
XIN/FIN
PLL600-x7
DESCRIPTION
The PLL600-27/-37 form a low cost family of XO
IC’s, designed to consume the lowest current on the
market for the 10MHz to 52MHz range. It accepts
fundamental resonant mode crystal input from 10 to
52MHz. Providing less than -130dBc at 10kHz offset
at 30MHz and with a very low jitter (2.5 ps RMS pe-
riod jitter) makes this chip ideal for applications re-
quiring low current frequency sources.
1
2
3
6
5
4
VDD
OE^
XOUT
^: denotes internal Pull-up
PLL600-x7
BLOCK DIAGRAM
SELECTION TABLE
XIN/FIN
XOUT
XTAL
OSC
CLK
OE
OE^
0
0
1
1
OSCSEL^*
0
1
0
1
OUTPUT
Disabled - osc. off
Disabled - osc. on
Enabled
Enabled
OSCSEL
^ Internal Pull-up, default value is ‘1’ when not connected.
* Not available in 6 pin SOT package.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 1
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
PIN/PAD DESCRIPTION
Name
XIN
N/C
GND
OSCSEL
CLK
VDD
OE
XOUT
Pin #
8 pin
SOIC
1
2
3
4
5
6
7
8
6 pin
SOT
4
n/a
2
n/a
1
6
5
3
Type
I
I
P
I
O
P
I
I
Description
Crystal input or reference clock input pin.
No connect.
Ground.
Disable mode select. See Table on page 1.
Output clock.
Power supply.
Output Enable input. See Table on page 1.
Crystal output.
OE and OSCSEL have internal pull-ups, so the default value is ‘1’ when not connected (OSCSEL not available on 6 pin package).
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Settling time
At power-up
(Vdd reaches 1.62V)
Disable to enable, osc. Off
Disable to enable, osc. On
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Frequency vs. VDD +/- 10%
Measured @ 50% V
DD
CONDITIONS
MIN.
10
TYP.
MAX.
52
10
10
500
UNITS
MHz
ms
ms
µs
ns
Output Clock Rise/Fall Time
VDD sensitivity
Output Clock Duty Cycle
1.15
2.4
0.8
45
50
0.8
55
ppm
%
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 2
Preliminary
3. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
PLL600-27/-37
MAX.
2.5
Ultra Low Current XO 10 MHz to 52 MHz
MIN.
TYP.
2.1
-80
-110
-130
-138
-145
CONDITIONS
With capacitive decoupling
between VDD and GND.
30MHz @100Hz offset
30MHz @1kHz offset
30MHz @10kHz offset
30MHz @100kHz offset
30MHz @1MHz offset
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
4. DC Specification
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
(at VDD = 3.3V)
Respectively for PLL600
-27/-37
Supply Current in tri-
state
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level (PLL600-27)
Output drive current
(PLL600-27)
Short Circuit Current
SYMBOL
CONDITIONS
At 10MHz, Cload=15pF
At 13.5MHz, Cload=15pF
At 17.7MHz, Cload=15pF
At 27MHz, Cload=15pF
At 48MHz, Cload=15pF
Output disabled, Osc. off
Output disabled, Osc. On
I
OH
= -12mA* (3.3V)
-37*, I
OH
= -12mA* (3.3V)
I
OL
= 12mA* (3.3V)
-37*, I
OL
= 12mA* (3.3V)
I
OH
= -4mA
At TTL level (3.3V)
(3.3V)
MIN.
TYP.
1.0 / 0.75
1.2
1.5
2.0
3.5
/ 0.8
/ 1.0
/ 1.2
/ 2.1
2
MAX.
1.1 / 0.9
1.3
1.6
2.1
3.6
/ 1.0
/ 1.1
/ 1.3
/ 2.2
4
520
UNITS
I
DD
mA
I
DD
V
DD
V
OH
V
OL
V
OHC
1.62
2.4
2.4
3.63
2.9
0.32
0.4
0.4
µA
µA
V
V
V
V
V
V
V
DD
– 0.4
12
17
±50
mA
mA
* Note:
PLL600-37 has non-standard CMOS VOH and VOL levels for lower current consumption, but meets CMOS input stage needs. PLL600-37
should be used to drive pure capacitive loads only.
5. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Maximum Sustainable Drive Level
Operating Drive Level
C0 (for frequencies below 30MHz)
C0 (for frequencies above 30MHz)
ESR
SYMBOL
F
XIN
C
L (xtal)
MIN.
10
TYP.
8.5
MAX.
52
200
UNITS
MHz
pF
µW
µW
pF
pF
Ω
50
5
4
R
S
30
Note:
A detailed crystal specification document is also available for this part
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 3
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
PACKAGE INFORMATION
8-PIN SOIC ( dimensions in mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
1.27 BSC
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
A
1
e
B
C
L
A
D
E
H
6-PIN SOIC ( dimensions in mm )
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 4
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PART NUMBER
PLL600-X7 x x
Part Number
Temperature
C=Commercial
I=Industrial
Package
S=SOIC
T=SOT
Order Number
PLL600-27SC
PLL600-27SC-R
PLL600-27TC
PLL600-37SC
PLL600-37SC-R
PLL600-37TC
Marking
P600-27
P600-27
A27A1
P600-37
P600-37
A37A2
SC
SC
SC
SC
Package Option
8-Pin
8-Pin
6-Pin
8-Pin
8-Pin
6-Pin
SOIC (Tube)
SOIC (Tape and Reel)
SOT (Bulk)
SOIC (Tube)
SOIC (Tape and Reel)
SOT (Bulk)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 5
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
