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PLL520-20

Description
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
File Size204KB,7 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet View All

PLL520-20 Overview

Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)

Preliminary
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
FEATURES
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100MHz – 200MHz (no PLL).
Low Injection Power for crystal 50uW.
Complementary outputs: CMOS, PECL or LVDS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Die thickness is 10 mil.
62 mil
DIE CONFIGURATION
65 mil
DNC
DNC
VDD
VDD
VDD
VDD
N/C
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
N/C
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OUTSEL^
XIN
XOUT
DNC
DNC
OE
CTRL
VCON
26
27
Die ID:
A1919-19B
15
28
14
13
29
12
DESCRIPTIONS
PLL520-20 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
DIE SPECIFICATIONS
Name
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
Size
Reverse side
Pad dimensions
Thickness
BLOCK DIAGRAM
OE
VCON
Oscillator
X+
X-
Q
Q
Amplifier
w/
integrated
varicaps
PLL520-20
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
OE_SELECT
(Pad #9)
0
1 (Default)
Pad #25
OUTSEL0
0
1
0
1
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 03/03/05 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
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