Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
FEATURES
•
•
•
•
•
•
•
•
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no multiplication).
Selectable OE logic.
Minimum bondwires required for VDD and GND.
Available outputs: PECL or LVDS.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DIE CONFIGURATION
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DESCRIPTIONS
PLL620-21 is an XO IC specifically designed to work
with high frequency fundamental and third overtone
crystals. Its design was optimized to tolerate higher
limits of interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It offers a selectable OE logic and is ideal
for XO applications requiring LVDS or PECL output
levels at high frequencies.
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DIE SPECIFICATIONS
Name
Size
Reverse side
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
#
.
)0 1 23 *
4 5 *
Pad dimensions
Thickness
/
/
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
Selected Output
LVDS
PECL (default)
Pad #30
OE_CTRL
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
0
1
Pad #25
OESEL
0
1
(default)
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Pad # 9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad # 30: Logical states defined by PECL levels if OUTSEL (pad # 9) is “1”
Logical states defined by CMOS levels if OUTSEL is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 07/15/05 Page 1
( ) *+ ,
Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
-65
-40
MAX.
7
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Load Capacitance
Shunt Capacitance
Oscillation Frequency
Recommended ESR
SYMBOL
C
L
C
0
OF
R
E
CONDITIONS
IC only
Fund. Or 3
rd
Overtone
MIN.
TYP.
4
MAX.
2
200
30
UNITS
pF
pF
MHz
Ω
120
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 07/15/05 Page 2
Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS
MIN.
3.13
TYP.
MAX.
100/80
3.47
UNITS
mA
V
%
mA
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
45
45
50
50
±50
55
55
4. Jitter specifications
PARAMETERS
Period jitter RMS at 155MHz
Period jitter peak-to-peak at 155MHz
Accumulated jitter RMS at 155MHz
Accumulated jitter peak-to-peak at 155MHz
Integrated jitter RMS at 155MHz
CONDITIONS
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
1,000,000 cycles.
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
20
3
25
0.3
MAX.
UNITS
ps
ps
ps
Note: Higher Q factor of 3
rd
overtone crystals will result in even better jitter performance.
5. Phase noise specifications
PARAMETERS
Phase Noise vs. carrier
with fund. crystal.
FREQUENCY
155.52MHz
@10Hz
-80
@100Hz
-110
@1kHz
-125
@10kHz
-143
@100kHz
-145
UNITS
dBc/Hz
Note: Higher Q factor of 3
rd
overtone crystals will result in even better phase noise performance.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 07/15/05 Page 3
Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
6
. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
1.1
1.2
3
±1
-5.7
V
out
= V
DD
or GND
V
DD
= 0V
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
C
L
= 10pF
50Ω
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 07/15/05 Page 4
Preliminary
PLL620-21
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
8. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
V
DD
– 1.620
MAX.
UNITS
V
V
9. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
www.phaselink.com
Rev 07/15/05 Page 5
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