EEWORLDEEWORLDEEWORLD

Part Number

Search

PLL650-09

Description
Low Cost Network LAN Clock
File Size225KB,5 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Compare View All

PLL650-09 Overview

Low Cost Network LAN Clock

PLL650-09
Low Cost Network LAN Clock
FEATURES
PIN CONFIGURATION
XIN
XOUT
G ND
VDD
50MHz
G ND
50MHz
1
2
16
15
VDD
VDD
N/C
G ND
G ND
GND
VDD
50MHz
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs fixed at 50MHz .
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 16-Pin 150mil SOIC
.
P LL 650-09
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTIONS
The PLL 650-09 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
accepts 25.0 MHz crystal, and produces multiple output
clocks for networking chips.
50MHz
BLOCK DIAGRAM
4
XIN
XOUT
XTAL
OS C
50MHz
C ontrol
Logic
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 09/19/02 Page 1

PLL650-09 Related Products

PLL650-09 PLL650-09SC PLL650-09SI PLL650-09SM
Description Low Cost Network LAN Clock Low Cost Network LAN Clock Low Cost Network LAN Clock Low Cost Network LAN Clock

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2532  528  2307  2020  2520  51  11  47  41  59 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号