• Internal series resistors to reduce switching noise
• ±12 mA device capability
• Low voltage operation
- V
DD
= 3.3 ± 0.3V
• 0.50 mm pitch, 56-Pin TSSOP package
1
Pin Configurations
NC
NC
Y1
GND
Y2
Y3
VDD
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VDD
Y16
Y17
GND
Y18
OE#
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Function Table
Inputs
OE#
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
Outputs
CLK
X
X
X
↑
↑
H
L
Ax
X
L
H
L
H
X
X
Yx
Z
L
H
L
H
Y
0(2)
Y
0(3)
GND
NC
A1
GND
A2
A3
VDD
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VDD
A16
A17
GND
A18
CLK
GND
56-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Notes:
1.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
Output level before the indicated steady-state
input conditions were established, provided that
CLK is HIGH before LE went LOW.
Output level before the indicated steady-state
input conditions were established.
2.
3.
Pin Description
Pin Names
OE#
CLK
LE
Ax
Yx
V
DD
GND
Description
Output Enable Input (Active Low)
Clock Input
Latch Enable Input
Data Input
Data Outputs
Supply Voltage
Ground
Block Diagram
OE#
CLK
LE
A1
1D
C1
CK
Y1
To 17 Other Channels
0713—09/23/02
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS162835
ICS162835
Advance Information
General Description
The ICS162835 low voltage 18-bit register combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched and clocked modes. Date flow is controlled by output-enable (OE#), latch enable (LE), and
clock (CLK) inputs. The device operates in transparent mode when LE is held high. The device operates in
clocked mode when LE is low and CLK is toggled. Data transfers from the inputs (A[18:1]) to outputs (Y[18:1])
on a positive edge transition of the clock. When OE# is low, the output state is enabled. When OE# is high,
the output port is in a high impedance state.
The 18-bit registered buffer is designed to operate with a 3.0V to 4.6V supply voltage.
All inputs support operation with standard LVTTL interface levels. This includes data inputs, clock inputs and
control inputs. Device outputs meet the requirements of the PC133 Registered DIMM specification. The device
functions as defined supports latched, registered and flow through modes of operations. The PC133
Specification requires only registered mode.
Package is a 56 thin shrink small-outline package as defined by JEDEC Publication, JEP95, MO-153.
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