ICSSSTV32852
General Description
The 24-bit-to-48-bit
ICSSSTV32852
is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and SSTL_2 I/
O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only.
ICSSSTV32852
supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the
logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET#
must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-
up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration
PIN NUMBER
R1,P1, N1, N2, M1, L2, L1, K1,
K2, J2, J1, H1, G1, G2, F1, F2,
E1, D1, D2, C1, C2, B1, A1,
A2
R6, P6, N6, N5, M6, L5, L6,
K6, K5, J5, J6, H6, G6, G5,
F6, F5, E6, D6, D5, C6, C5,
B6, A6, A5
E2, B3, D3, G3, J3, L3, M3,
P3, B4, D4, G4, J4, L4, M4,
P4, E5
B2, M2, P2, C3, E3, F3, H3,
K3, N3, C4, E4, F4, H4, K4,
N4, B5, M5, P5
W4, V4, U4, W5, W6, V5, T4,
V6, U6, U5, T6, T5, W3, V3,
U3, W2, W1, V2, T3, V1, U1,
U2, T1, T2
A3
A4
H2, H5, R2, R5
R3
R4
PIN NAME
Q (24:1)A
TYPE
OUTPUT
Data output
DESCRIPTION
Q (24:1)B
OUTPUT
Data output
GND
PWR
Ground
VDDQ
PWR
Output supply voltage, 2.5V nominal
D (24:1)
CLK
CLK#
VDD
RESET#
VREF
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 1.25V nominal
0513F—05/13/03
2
ICSSSTV32852
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage
1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clamp Current . . . . . . . . . . . . . . . . . . . .
Output Clamp Current . . . . . . . . . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . .
VDD, VDDQ or GND Current/Pin . . . . . . . . . .
Package Thermal Impedance
3
...............
–65°C to +150°C
-0.5 to 3.6V
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
±50 mA
±50mA
±50mA
±100mA
55°C/W
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH (DC)
V
IH (AC)
V
IL (DC)
V
IL (DC)
V
IH
V
IL
V
ICR
V
ID
V
IX
I
OH
I
OL
T
A
1
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
Termination Voltage
Input Voltage
DC Input High Voltage
AC Input High Voltage
Data Inputs
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
RESET#
Input Low Voltage Level
Common mode Input Range
CLK, CLK#
Differential Input Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
MIN
2.3
2.3
1.15
V
REF
- 0.04
0
V
REF
+ 0.15
V
REF
+ 0.31
TYP
2.5
2.5
1.25
V
REF
MAX
2.7
2.7
1.35
V
REF
+ 0.04
V
DDQ
UNITS
V
REF
- 0.15
V
REF
- 0.31
1.7
0.97
0.36
(V
DDQ
/2) - 0.2
0.7
1.53
V
(V
DDQ
/2) + 0.2
19
19
70
mA
°C
0
Guarenteed by design, not 100% tested in production.
0513F—05/13/03
3
FPGA/CPLD
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EEWORLD
