PLL502-03
Low Phase Noise VCXO (48MHz to 100MHz)
FEATURES
•
•
•
•
•
•
•
•
•
•
VCXO output for the 48MHz to 100MHz range
Low phase noise (-130 dBc @ 10kHz offset at
48MHz).
CMOS output.
12 to 25MHz crystal input.
Integrated variable capacitors.
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
Wide pull range (+/- 250 ppm).
Low jitter (RMS): 3.5ps period.
3.3V operation.
Available in 8-Pin SOIC.
PIN CONFIGURATION
XOUT
N/C
VCON
GND
1
2
3
4
8
7
6
5
XIN
OE^
VDD
CLK
Note: ^ denotes internal pull up
OUTPUT RANGE
MULTIPLIER
X4
FREQUENCY
RANGE
48 - 100MHz
OUTPUT
BUFFER
CMOS
PLL502-03
DESCRIPTION
The PLL502-03 is a low cost, high performance and
low phase noise VCXO for the 48 to 100MHz range,
providing less than -130dBc at 10kHz offset at
48MHz. The very low jitter (3.5ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 25MHz (fundamental resonant
mode).
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 1
PLL502-03
Low Phase Noise VCXO (48MHz to 100MHz)
PIN DESCRIPTIONS
Name
XOUT
N/C
VCON
GND
CLK
VDD
OE
XIN
Number
1
2
3
4
5
6
7
8
Type
I
-
I
P
O
P
I
I
Not connected.
Voltage Control input.
Ground.
Output clock.
+3.3V power supply.
Description
Crystal output. See Crystal Specifications on page 3.
Output enable input. Disables (tri-state) output when low. Internal pull-up
enables output by default if pin is not connected to low.
Crystal input. See Crystal Specifications on page 3.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. DC Electrical Specifications
PARAMETERS
Supply Current, Dynamic, with
Loaded Outputs
Operating Voltage
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Short Circuit Current
VCXO Control Voltage
SYMBOL
I
DD
V
DD
I
OH
I
OL
I
OH
I
OL
VCON
CONDITIONS
F
XIN
= 12 - 25MHz
Output load of 10pF
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
MIN.
TYP.
16
MAX.
20
3.63
UNITS
mA
V
mA
mA
mA
mA
mA
V
2.97
30
30
10
10
±50
0
3.3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 2
PLL502-03
Low Phase Noise VCXO (48MHz to 100MHz)
3. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
Output Clock Duty Cycle
SYMBOL
CONDITIONS
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 50% V
DD
MIN.
12
TYP.
2.4
1.2
MAX.
25
UNITS
MHz
ns
45
50
55
%
4. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
500
±200
150
10
2000
25
0V
≤
VCON
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
5. Jitter and Phase Noise specification
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
with capacitive decoupling
between VDD and GND.
48MHz @100Hz offset
48MHz @1kHz offset
48MHz @10kHz offset
48MHz @100kHz offset
48MHz @1MHz offset
MIN.
TYP.
3.5
-100
-123
-130
-125
-125
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
6. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
C0/C1
ESR
SYMBOL
F
XIN
C
L (xtal)
R
S
MIN.
12
TYP.
9.5
MAX.
25
250
30
UNITS
MHz
pF
-
Ω
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 3
PLL502-03
Low Phase Noise VCXO (48MHz to 100MHz)
PACKAGE INFORMATION
8 PIN SOIC (in mm)
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.47
1.73
0.10
0.25
0.33
0.51
0.19
0.25
4.80
4.95
3.80
4.00
5.80
6.20
0.38
1.27
1.27 BSC
E
H
D
A
A1
e
B
C
L
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-03 (H) X C
PART NUMBER
Optional High Drive
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
S=SOIC
Order Number
PLL502-03SC
PLL502-03SC -R
PLL502-03HSC
PLL502-03HSC -R
Marking
P502-03SC
P502-03SC
P502-03HSC
P502-03HSC
Package Option
8-Pin
8-Pin
8-Pin
8-Pin
SOIC
SOIC
SOIC
SOIC
(Tube)
(Tape and Reel)
(Tube)
(Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 4
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
