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PLL502-39UQI-R

Description
750kHz - 800MHz Low Phase Noise Multiplier VCXO
File Size241KB,6 Pages
ManufacturerPLL (PhaseLink Corporation)
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PLL502-39UQI-R Overview

750kHz - 800MHz Low Phase Noise Multiplier VCXO

PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Inverted LVDS signal Output Enable selector.
Wide pull range (+/-200 ppm)
Selectable 1/16 to 32x frequency multiplier.
3.3V operation.
Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
SEL0^
10
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
XIN
VDD
8
7
6
5
GND
CLKC
VDD
CLKT
PLL502-39U
1
2
3
4
DESCRIPTION
VCON
GND
GND
The PLL502-39U (LVDS) is a high performance and
low phase noise VCXO clock IC. It provides phase
noise performance as low as –125dBc at 10kHz off-
set (at 155MHz), by multiplying the input crystal fre-
quency up to 32x. The wide pull range (+/- 200 ppm)
and very low jitter makes this ideal for a wide range
of applications, including SONET/SDH and FEC.
PLL502-39 accepts fundamental parallel resonant
mode crystals input from 12 to 25MHz.
Note: ^ designates Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-39U
OE
1
0 (Default)
Tri-state
GND
State
Output enabled
BLOCK DIAGRAM
SEL
OE
VCON
Oscillator
XIN
XOUT
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
CLKC
CLKT
PLL by-pass
PLL502-39U
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 1

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Description 750kHz - 800MHz Low Phase Noise Multiplier VCXO 750kHz - 800MHz Low Phase Noise Multiplier VCXO 750kHz - 800MHz Low Phase Noise Multiplier VCXO 750kHz - 800MHz Low Phase Noise Multiplier VCXO 750kHz - 800MHz Low Phase Noise Multiplier VCXO
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