PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83054I-01
4-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
G
ENERAL
D
ESCRIPTION
The ICS83054I-01 is a 4-bit, 2:1, Single-ended Mul-
tiplexer and a member of the HiPerClockS™fam-
HiPerClockS™
ily of High Performance Clock Solutions from ICS.
The ICS83054I-01 has two selectable single-ended
clock inputs and four single-ended clock outputs.
The output has a V
DDO
pin which may be set at 3.3V, 2.5V, or
1.8V, making the device ideal for use in voltage translation ap-
plications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug. Possible applications include systems with up to four
transceivers which need to be independently set for different
rates. For example, a board may have four transceivers, each
of which need to be independently configured for 1 Gigabit
Ethernet or 1 Gigabit Fibre Channel rates. Another possible
application may require the ports to be independently set for
FEC (Forward Error Correction) or non-FEC rates. The device
operates up to 250MHz and is packaged in a 16 TSSOP.
F
EATURES
• 4-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15Ω (V
DDO
=3 .3V)
• Maximum output frequency: 250MHz
• Propagation delay: 2.5ns (typical)
• Input skew: 45ps (typical)
• Part-to-part skew: TBD
•
Additive phase jitter, RMS (12KHz - 20MHz):
0.07ps (typical)
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
ICS
B
LOCK
D
IAGRAM
SEL0 Pulldown
P
IN
A
SSIGNMENT
SEL3
Q3
V
DDO
GND
Q2
SEL2
CLK1
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0
Q0
V
DDO
GND
Q1
SEL1
CLK0
OE
CLK0
Pulldown
0
Q0
CLK1
Pulldown
1
0
Q3
ICS83054I-01
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
1
SEL3 Pulldown
OE
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83054I-01
4-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
11, 16
2, 5, 9, 12, 15
3, 14
4, 13
7, 10
8
Name
SEL3, SEL2,
SEL1, SEL0
Q3, Q2, Q1, Q0
V
DDO
GND
CLK1, CLK0
V
DD
Type
Input
Output
Power
Power
Input
Power
Description
Clock select inputs. See Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pins.
Power supply ground.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable. When LOW, outputs are in HIGH impedance state.
9
OE
Input
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
11
15
Maximum
Units
pF
KΩ
KΩ
pF
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
SEL3
0
0
0
Control Inputs
SEL2
S E L1
0
0
0
0
0
1
Outputs
SEL0
0
1
0
Q3
CLK0
CLK0
CLK0
Q2
CLK0
CLK0
CLK0
Q1
CLK0
CLK0
CLK1
Q0
CLK0
CLK1
CLK0
•
•
•
1
1
1
1
1
1
0
1
1
1
0
1
CLK1
CLK1
CLK1
CLK1
CLK1
CLK1
•
•
•
CLK0
CLK1
CLK1
CLK1
CLK0
CLK1
83054AGI-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 24, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83054I-01
4-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
A
= -40°C
TO
85°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%,
OR
2.5V±5%,
OR
1.8V±0.2V,
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
1.6
Typical
3.3
3.3
2.5
1.8
32
4
Maximum
3.465
3.465
2.625
2.0
Units
V
V
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5%,
OR
1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
30
4
Maximum
2.625
2.625
2.0
Units
V
V
V
mA
mA
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83054I-01
4-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
Parameter
CLK0, CLK1
V
IH
Input High Voltage
OE,
SEL0:SEL3
CLK0, CLK1
V
IL
Input Low Voltage
OE,
SEL0:SEL3
Input High Current
CLK0, CLK1,
SEL0:SEL3
OE
CLK0, CLK1,
SEL0:SEL3
OE
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output HighVoltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
-5
-150
2.6
1.8
V
DD
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
2
1.7
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
1.3
0.7
150
5
Units
V
V
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
I
IH
I
IL
Input Low Current
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
Par t-to-Par t Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
Test Conditions
Minimum
Typical
Maximum
250
2.5
2.65
45
TBD
Integration Range:
12KHz - 20MHz
20% to 80%
0.07
535
50
5
5
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
t
sk(i)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
t
DIS
@100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1A: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83054AGI-01
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 24, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83054I-01
4-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
Par t-to-Par t Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
Test Conditions
Minimum
Typical
Maximum
250
2.7
2.7
38
TBD
Integration Range:
12KHz - 20MHz
20% to 80%
0.04
550
50
5
5
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
t
sk(i)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
t
DIS
@100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1A: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
Par t-to-Par t Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
Test Conditions
Minimum
Typical
Maximum
250
3
3
38
TBD
Integration Range:
12KHz - 20MHz
20% to 80%
0.05
595
50
5
5
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
t
sk(i)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
t
DIS
@100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1A: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83054AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 24, 2004
5
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