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ICS8432DY-101

Description
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
File Size186KB,18 Pages
ManufacturerICS ( IDT )
Websitehttp://www.icst.com
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ICS8432DY-101 Overview

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
Output frequency range: 25MHz to 700MHz
VCO range: 250MHz to 700MHz
Accepts any single-ended input signal on CLK input
with resistor bias on nCLK input
Parallel interface for programming counter
and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8432-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
HiPerClockS™
synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8432-101 has a selectable
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input
accepts LVCMOS or LVTTL input levels and translates them
to 3.3V LVPECL levels. The CLK, nCLK pair can accept most
standard differential input levels. The VCO operates at a
frequency range of 250MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input differ-
ential or single ended reference frequency. The VCO and
output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The low phase
noise characteristics of the ICS8432-101 makes it an ideal
clock source for Gigabit Ethernet and SONET applications.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
nCLK
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
1
÷
1
÷
2
÷
4
÷
8
FOUT0
nFOUT0
FOUT1
nFOUT1
N0
N1
nc
V
EE
ICS8432-101
21
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8432DY-101
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 1, 2005

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Description 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
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