PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840001-32
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
One LVCMOS/LVTTL output, 15Ω typical output
impedence and one reference clock output
•
40MHz, 10pF parallel resonant crystal
•
Output frequencies: 100MHz or 106.25MHz
•
RMS phase jitter @ 106.25MHz, using a 40MHz crystal
(637kHz - 5MHz): 0.78ps (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Availabe in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS840001-32 is a two output LVCMOS/
LVTTL Synthesizer and is a member of the
HiPerClockS™
HiPerClocks
TM
family of high perfor mance
devices from ICS. The device uses a 40MHz
crystal to provide a 40MHz reference clock
output and to synthesize a 100MHz or 106.25MHz
output. The ICS840001-32 has excellent <1ps phase
jitter performance over the 637kHz – 5MHz integration
range. The ICS840001-32 is packaged in a 3mm x 3mm
16-pin VFQFN, making it ideal for use on space con-
strained boards.
IC
S
F
UNCTION
T
ABLE
Inputs
Crystal Frequency
(MHz)
40
40
Outputs
SEL Input
0
1
Q Output
Frequency (MHz)
100
106.25
REF_OUT
Frequency (MHz)
40
40
B
LOCK
D
IAGRAM
40MHz
P
IN
A
SSIGNMENT
V
DDA
GND
nc
nc
REF_OUT
V
DD
1
XTAL_OUT 2
XTAL_IN
16 15 14 13
12
11
10
9
5
GND
Q
V
DDO
_
Q
V
DD
REF_OUT
OSC
XTAL_OUT
SEL
(Pullup)
Synthesizer
100MHz or
106.25MHz
XTAL_IN 3
SEL 4
6
nc
Q
7
V
DDO
_
REF
_
OUT
8
GND
ICS840001-32
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
840001CK-32
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 23, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840001-32
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Type
Power
Input
Input
Power
Pullup
Description
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Select input. LVCMOS/LVTTL interface levels.
Power supply ground.
No connect.
Output supply pin for REF_OUT output
Single-ended three-state reference clock output.
LVCMOS/LVTTL interface levels. 15
Ω
typical output impedance.
Output supply pin for Q output.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15
Ω
typical output impedance.
Analog supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 10
2, 3
4
5, 8, 13
6, 14, 15
7
9
11
12
16
Name
V
DD
XTAL_OUT,
XTAL_IN
SE L
GND
nc
V
DDO_REF_OUT
REF_OUT
V
DDO_Q
Q
V
DDA
Unused
Power
Output
Power
Output
Power
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Output Impedance
V
DD
, V
DDA,
V
DDO_REF_OUT,
V
DDO_Q
=
3.465V
Test Conditions
Minimum
Typical
4
8
51
15
Maximum
Units
pF
pF
kΩ
Ω
840001CK-32
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840001-32
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
51.5°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_REF_OUT
= V
DDO_Q
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
70
25
12
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_REF_OUT
= V
DDO_Q
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
V
V
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO_x
/2 See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
10
Test Conditions
Minimum
Typical
Fundamental
40
50
7
100
MH z
Ω
pF
µW
Maximum
Units
840001CK-32
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840001-32
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Test Conditions
REF_OUT
Q
f_SEL = 0
f_SEL = 1
100MHz, Integration Range:
637kHz to 5MHz
106.25MHz, Integration Range:
637kHz to 5MHz
20% to 80%
Minimum
Typical
100
106.25
0.83
0.78
900
50
Maximum
Units
MHz
MHz
ps
ps
ps
%
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_REF_OUT
= V
DDO_Q
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
OUT
Output Frequency
t
jit(Ø)
t
R
/ t
F
RMS Phase Jitter (Random)
Output Rise/Fall Time
odc
Output Duty Cycle
All parameters are characterized @ 100MHz and 106.25MHz.
840001CK-32
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 23, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840001-32
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
0
-10
-20
-30
-40
-50
Fibre Channel Filter
➤
106.25MHz
Raw Phase Noise Data
RMS Phase Jitter (Random)
637kHz to 5MHz = 0.78ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1k
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
10k
100k
1M
840001CK-32
www.icst.com/products/hiperclocks.html
5
➤
O
FFSET
F
REQUENCY
(H
Z
)
REV. A NOVEMBER 23, 2005
PCB Design
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