PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER WITH
F
ANOUT
B
UFFER
F
EATURES
•
6 LVCMOS/LVTTL outputs
•
Crystal oscillator interface
•
Output frequency range: 53.125MHz to 125MHz
•
Crystal input frequency: 25MHz and 25.5MHz
•
RMS phase jitter at 106.25, using a 25.5MHz crystal
(637KHz to 10MHz): 3.25ps
•
Phase noise:
Offset
Noise Power
100Hz ................. -100 dBc/Hz
1KHz ................. -115 dBc/Hz
10KHz ................. -125 dBc/Hz
100KHz ................. -127 dBc/Hz
•
3.3V core, outputs may either be 3.3V, 2.5V or 1.8V
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS84025 is a Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer with Fanout Buffer and
HiPerClockS™
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
VCO frequency is programmed in steps equal
to the value of the crystal frequency. The VCO and
output frequency can be programmed using the feedback and
output frequency select pins. The low phase noise character-
istics of the ICS84025 make it an ideal clock source for Fibre
Channel 1 and Gigabit Ethernet applications.
,&6
F
UNCTION
T
ABLE
Inputs
MR
1
0
0
0
0
F_SEL1
X
0
0
1
1
F_SEL0
X
0
1
0
1
25.5MHz
25.5MHz
25MHz
25MHz
XTAL
Output Frequency
F_OUT
LOW
53.125MHz
106.25MHz
62.5MHz
125MHz
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
Q0
GND
Q1
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
Q5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
GND
V
DDA
V
DD
PLL_SEL
GND
nc
V
DDO
XTAL1
OSC
XTAL2
0
1
Output
Divider
6
/
Q0:Q5
PLL
Feedback
Divider
ICS84025
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL1
PLL_SEL
MR
F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84025EM
www.icst.com/products/hiperclocks.html
1
REV. A APRIL 16, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER WITH
F
ANOUT
B
UFFER
Type
Power
Output
Power
Output
Output
Output
Output
Output
Unused
Input
Power
Power
Input
Input
Pullup
Description
Output supply pins.
Clock output. LVCMOS/LVTTL interface levels.
Power supply ground.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
Clock output. LVCMOS/LVTTL interface levels.
No connect.
Selects between the PLL and cr ystal inputs as the input
to the dividers. When HIGH, selects PLL. When LOW,
selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels.
Core supply pin.
Analog supply pin.
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
Pulldown
internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Pullup
Output frequency select pin. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 5, 9, 13
2
3, 7, 11, 15, 19
4
6
8
10
12
14
16
17
18
20, 21
22
Name
V
DDO
Q0
GND
Q1
Q2
Q3
Q4
Q5
nc
PLL_SEL
V
DD
V
DDA
XTAL2, XTAL1
MR
23
24
F_SEL1
F_SEL0
Input
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
V
DD
= 3.465V, V
DDO
= 1.95V
51
51
TBD
TBD
TBD
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
pF
pF
pF
84025EM
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 16, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER WITH
F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
1.65
Typical
3.3
3.3
3.3
2.5
1.8
71
15
70
Maximum
3.465
3.465
3.465
2.625
1.95
Units
V
V
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
MR, F_SEL1
PLL_SEL, F_SEL0
MR, F_SEL1
PLL_SEL, F_SEL0
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
V
DDO
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.15V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
-5
-150
2.6
1.8
V
DDO
- 0.45
0.5
0.5
0.45
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
V
V
V
V
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
84025EM
Test Conditions
Minimum
25
Typical Maximum
25.5
70
7
Units
MHz
Ω
pF
REV. A APRIL 16, 2003
Fundamental
www.icst.com/products/hiperclocks.html
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER WITH
F
ANOUT
B
UFFER
Test Conditions
Minimum
53.125
50
TBD
20% to 80%
300
50
t
PERIOD
/2 - TBD
t
PERIOD
/2 + TBD
700
Typical
Maximum
125
Units
MHz
ps
ps
ps
%
ps
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
F
OUT
Output Frequency
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
Output Pulse Width
t
jit(cc)
t
sk(o)
t
R
/ t
F
odc
t
PW
PLL Lock Time
1
ms
t
LOCK
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
F
OUT
Output Frequency
Cycle-to-Cycle Jitter ; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
Output Pulse Width
t
PERIOD
/2 - TBD
20% to 80%
300
50
t
PERIOD
/2 + TBD
Test Conditions
Minimum
53.125
30
TBD
700
Typical
Maximum
125
Units
MHz
ps
ps
ps
%
ps
t
jit(cc)
t
sk(o)
t
R
/ t
F
odc
t
PW
PLL Lock Time
1
ms
t
LOCK
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.15V, T
A
= 0°C
TO
70°C
Symbol Parameter
F
OUT
Output Frequency
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
Output Pulse Width
t
PERIOD
/2 - TBD
20% to 80%
300
50
t
PERIOD
/2 + TBD
Test Conditions
Minimum
53.125
30
TBD
700
Typical
Maximum
125
Units
MHz
ps
ps
ps
%
ps
t
jit(cc)
t
sk(o)
t
R
/ t
F
odc
t
PW
PLL Lock Time
1
ms
t
LOCK
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84025EM
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 16, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER WITH
F
ANOUT
B
UFFER
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
25MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
P
HASE
N
OISE
-60
(
dBc
)
H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
125MHz
62.5MHz
1k
10k
100k
1M
10M
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
25.5MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
P
HASE
N
OISE
-60
(
dBc
)
H
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
106.25MHz
53.125MHz
Z
1k
10k
100k
1M
10M
O
FFSET
F
REQUENCY
(H
Z
)
84025EM
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5
REV. A APRIL 16, 2003
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