PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
F
EATURES
• One 3.3V LVPECL output pair and
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
<1ps (typical) design target
• Supply modes:
V
CC
/V
CCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS843001I-23 is a highly versatile, low
phase noise LVPECL/LVCMOS Synthesizer
HiPerClockS™
which can generate low jitter reference clocks
for a variety of communication applications
and is a member of the HiPerClocks
TM
family
of high performance clock solutions from ICS.
The dual crystal interface allows the synthesizer to
support up to three communication standards in a given
application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb
Ethernet and Fibre Channel using a 25MHz crystal). The
rms phase jitter performance is typically less than 1ps, thus
making the device acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
IC
S
B
LOCK
D
IAGRAM
3
N2:N0
SEL0
Pulldown
P
IN
A
SSIGNMENT
SEL1
Pulldown
N
XTAL_IN0
000
001
010
011
100
101
110
111
÷2
÷4
÷5
÷6
÷8
(default)
÷10
÷12
÷16
OSC
XTAL_OUT0
XTAL_IN1
00
11
OSC
XTAL_OUT1
CLK
Pulldown
01
Phase
Detector
VCO
10
01
00
V
CCO
_
LVCMOS
N0
N1
N2
V
CCO
_
LVPECL
Q
nQ
Q
V
EE
V
CCA
nQ
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF_OUT
V
EE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
CLK
XTAL_IN0
XTAL_OUT0
10
11
000
001
010
011
100
111
M
÷44
÷45
÷48
÷50
÷51
÷64
(default)
ICS843001I-23
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
MR
Pulldown
M2:M0
Pullup
3
REF_OUT
OE_REF
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843001AGI-23
www.icst.com/products/hiperclocks.html
1
REV. B JANUARY 6, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
Type
Description
Output supply pin for LVCMOS/LVTTL REF_OUT output.
Pulldown Output divider select pins. See Table 3C.
LVCMOS/LVTTL interface levels.
Pullup
Output supply pin for LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Pulldown LVCMOS/LVTTL clock input.
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q to go low and the inver ted output nQ to
Pulldown
go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Feedback divider select pins. See Table 3B.
Pullup
LVCMOS/LVTTL interface levels.
Reference clock output enable. Default Low. See Table 3E.
Pulldown
LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6, 7
8, 23
9
10
11
12
13
14
15
16, 17
18
Name
V
CCO_CMOS
N0, N1
N2
V
CCO_LVPECL
Q, nQ
V
EE
V
CCA
V
CC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
CLK
SEL0, SEL1
MR
Input
Input
Power
Ouput
Power
Power
Power
Input
Input
Input
Input
Input
Power
19, 20 , 21
22
24
M0, M1, M2
OE_REF
REF_OUT
Input
Input
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
out
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
REF_OUT
5
Test Conditions
Minimum
Typical
4
51
51
7
12
Maximum
Units
pF
kΩ
kΩ
Ω
843001AGI-23
www.icst.com/products/hiperclocks.html
2
REV. B JANUARY 6, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
Output Frequency
(MHz)
74.25
74.25
155.52
622.08
311.04
125
156.25
25 0
312.5
625
187.5
100
150
75
106.25
159.375
212.5
T
ABLE
3A. C
OMMON
C
ONFIGURATIONS
T
ABLE
Input
XTAL Input (MHz)
27
24.75
19.44
19.44
19.44
25
25
25
25
25
25
25
25
25
25
25
25
Feedback
Divider
44
48
64
64
64
50
50
50
50
50
45
48
48
48
51
51
51
VCO (MHz)
1188
1188
1244.16
1244.16
1244.16
1250
1250
1250
1250
1250
1125
1200
1200
1200
1275
1275
1275
N Divider Value
16
16
8
2
4
10
8
5
4
2
6
12
8
16
12
8
6
Application
HDTV
HDTV
SONET
SONET
SONET
GigE
10 GigE
GigE
XGMII
10 GigE
12 GigE
PCI Express
SATA
SATA
Fibre Channel
10 Gig Fibre Channel
4 Gig Fibre Channel
T
ABLE
3B. P
ROGRAMMABLE
M O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
M2
0
0
0
0
1
1
M1
0
0
1
1
0
1
M0
0
1
0
1
0
1
64
M Divider
Value
44
45
48
50
51
(default)
T
ABLE
3C. P
ROGRAMMABLE
N O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divide Value
2
4
5
6
8
(default)
10
12
16
Input Frequency
Minimum
25.5
24.9
23.3
22.4
22.0
17.5
Maximum
29.54
28.88
27.08
26.0
25.49
20.31
T
ABLE
3D. B
YPASS
M
ODE
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Reference Input
XTAL0
XTAL1
CL K
CLK
PLL Mode
Active
Active
Active
Bypass
T
ABLE
3E. OE_REF O
UTPUT
F
UNCTION
T
ABLE
Inputs
OE_REF
0
1
Output
REF_OUT
Hi-Z
Active
843001AGI-23
www.icst.com/products/hiperclocks.html
3
REV. B JANUARY 6, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-0.5V to V
CCO
+ 0.5V
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, V
O
(LVCMOS)
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVPECL,
V
CCO_LVCMOS
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_LVPECL
V
CCO_LVCMOS
I
EE
I
CCA
I
CCO_LVPECL
I
CCO_LVCMOS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
Test Conditions
Minimum
3.135
3.135
3.135
3.135
Typical
3.3
3.3
3.3
3.3
TBD
TBD
5
TBD
TBD
Maximum
3.465
3.465
3.465
3.465
Units
V
V
V
V
mA
mA
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO_LVPECL,
V
CCO_LVCMOS
= 2.5V±5%,
TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_LVPECL
V
CCO_LVCMOS
I
EE
I
CCA
I
CCO_LVPECL
I
CCO_LVCMOS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.625
2.625
Typical
3.3
3.3
2.5
2.5
TBD
TBD
TBD
TBD
TBD
Maximum
3.465
3.465
2.625
2.625
Units
V
V
V
V
mA
mA
mA
mA
mA
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
843001AGI-23
www.icst.com/products/hiperclocks.html
4
REV. B JANUARY 6, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001I-23
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL/LVCMOS
F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
2.625
2.625
2.625
2.625
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
Typical
2.5
2.5
2.5
2.5
TBD
TBD
5
TBD
TBD
Maximum
2.625
2.625
2.625
2.625
Units
V
V
V
V
mA
mA
mA
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVPECL,
V
CCO_LVCMOS
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_LVPECL
V
CCO_LVCMOS
I
EE
I
CCA
I
CCO_LVPECL
I
CCO_LVCMOS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Output Supply Current
T
ABLE
4D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS
= 3.3V±5%
OR
2.5V±5%,
OR
V
CC
= V
CCA
= 3.3V±5%, V
CCO_LVCMOS
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
N2, M0:M2
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
N2, M0:M2
REF_OUT
REF_OUT
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V
or 2.625V
V
CC
= V
IN
= 3.465V
or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CCO_LVCMOS
= 3.465V
V
CCO_LVCMOS
= 2.625V
V
CCO_LVCMOS
= 3.465V
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
5
-5
-150
2.6
1.8
0.5
TBD
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V/ns
I
IH
Input
High Current
I
IL
Input
Low Current
V
OH
V
OL
Output High
Voltage; NOTE 1
Output Low
Voltage; NOTE 1
or 2.625V
Input Edge Rate CLK
20% - 80%
Δ
V/
ΔT
NOTE 1: Output terminated with 50
Ω
to V
CCO _LVCMOS
/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram" diagrams.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVPECL
= 3.3V±5%
OR
2.5V±5%,
OR
V
CC
= V
CCA
= 3.3V±5%, V
CCO_LVPECL
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO_LVPECL
- 1.4
V
CCO_LVPECL
- 2.0
0.6
Typical
Maximum
V
CCO_LVPECL
- 0.9
V
CCO_LVPECL
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_LVPECL
- 2V.
843001AGI-23
www.icst.com/products/hiperclocks.html
5
REV. B JANUARY 6, 2006
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