SI5344H-D05895-GMR datasheet, PDF

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SI5344H-D05895-GMR: DescriptionClock Synthesizer / Jitter Cleaner 100G/400G Coherent Optics Clock, 2-Output, <2.7GHz, Jitter Attenuator, DCO; Categorysemiconductor Analog mixed-signal IC; File Size1MB，56 Pages; ManufacturerSilicon Laboratories

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SI5344H-D05895-GMR Overview

Clock Synthesizer / Jitter Cleaner 100G/400G Coherent Optics Clock, 2-Output, <2.7GHz, Jitter Attenuator, DCO

SI5344H-D05895-GMR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Synthesizer / Jitter Cleaner

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Si5344H/42H Rev D

I G H

-F

R E Q U E N C Y

, U

LTRA

-L

O W

I T T E R

T T E N U A T O R

L O C K

W I T H

IG ITA LLY

- C

O N T R O L L E D

S C I L L A T O R

Features



High-speed outputs generate an



ultra-low jitter output up to 2.75 GHz

Up to four Multi-Synth outputs



generate any frequency up to

717.5 MHz



Input frequency range:



8 kHz to 750 MHz



Maximum Output frequency:





High-Frequency Mode: 2.75 GHz





MultiSynth Mode: 717.5 MHz

Jitter performance:

High Frequency Mode:

<50 fs typ (1 MHz–40 MHz)



MultiSynth Mode:

<150 fs typ (12 kHz–20 MHz)



Programmable jitter attenuation



bandwidth: 10 Hz to 4 kHz

Highly configurable outputs



compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL with

programmable voltage swing and



common mode





LVPECL-only in High Frequency



Mode



Status monitoring (LOS, OOF, LOL)

Hitless input clock switching:

automatic or manual

Automatic free-run and holdover

modes

Glitchless on the fly output

frequency changes

Locks to gapped clock inputs

DCO mode: as low as 0.001 ppb

steps.

Core voltage



: 1.8 V ±5%



DDA

3.3 V ±5%

Independent output supply pins:

3.3 V, 2.5 V, or 1.8 V

Serial interface: I

C or SPI

In-circuit programmable with

non-volatile OTP memory

ClockBuilder Pro

software

simplifies device configuration

Si5342H: 2 input, 2 output, QFN44

Si5344H, 2 input, 4 output, QFN44

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

Ordering Information:

See Section 7.

Pin Assignments

Si5342H 44QFN

Top View

I2C_SEL

RSVD_GND

VDDS

VDD

IN0

VDD

IN1

IN_SEL0

VDDA

INTR

VDD

LOS1

LOS0

VDDS

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

Applications



GND

Pad

100G/200G/400G Optical

Transceivers



Wireless base-stations

VDDA

OUT0

VDD

SDA/SDIO

A1/SDO

A0/CS

RST

SDA/SDIO

A1/SDO

A0/CS

Rev. 1.0 9/16

VDDO0

OUT0

SCLK

OUT0

VDD

RST

This specialized jitter attenuating clock multiplier combines fourth-generation

DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high

data rate coherent optical transceiver design. Up to four outputs can be assigned

to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase

jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode

any-frequency outputs when added frequency flexibility is required, such as

clocking Forward Error Correction (FEC) while still delivering <150 fs-rms typical

phase jitter (12 kHz-20 MHz). The Si5344H and Si5342H also feature DCO-

control with as low as 0.001 ppb step control and locks to gapped clock inputs.

These devices are programmable via a serial interface with in-circuit

programmable non-volatile memory (NVM) so that they always power up with a

known frequency configuration. The loop filter is fully integrated on-chip

eliminating the risk of potential noise coupling associated with discrete solutions.

Programming the Si5342H/44H is made easy with Silicon Labs’

ClockBuilderPro

software. Factory preprogrammed devices are also available.

Si5344H 44QFN

Top View

I2C_SEL

IN_SEL1

VDDO3

VDDO0

OUT0

SCLK

Description

OUT3

IN1

IN_SEL0

XGND

VDDA

OUT3

VDD

IN0

VDD

INTR

VDD

OUT2

VDDO2

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

GND

Pad

Si5344H/42H

Si5344H/42H

ABLE

ON TENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6. Inputs (IN0, IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for

Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

8.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Rev. 1.0

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