Integrated
Circuit
Systems, Inc.
ICS84320I-01
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
•
Output frequency range: 77.5MHz to 780MHz
•
Crystal input frequency range: 14MHz to 40MHz
•
VCO range: 620MHz to 780MHz
•
Parallel or serial interface for programming counter
and output dividers
•
Duty cycle: 44% - 56% (N > 1)
•
RMS period jitter: 2.0ps (typical)
•
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12kHz to 20MHz): 2.38ps (typical)
•
RMS phase noise at 155.52MHz (typical)
Offset
Noise Power
100Hz ................ -90.5 dBc/Hz
1kHz ............... -114.2 dBc/Hz
10kHz ............... -123.6 dBc/Hz
100kHz ............... -128.1 dBc/Hz
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both, Standard and RoHS/Lead-Free
compliant packages
G
ENERAL
D
ESCRIPTION
The ICS84320I-01 is a general purpose, dual
output Crystal-to-3.3V Differential LVPECL
HiPerClockS™
High Frequency Synthesizer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS84320I-01
has a selectable TEST_CLK or crystal inputs. The VCO
operates at a frequency range of 620MHz to 780MHz. The
VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. The VCO
and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The
low phase noise characteristics of the ICS84320I-01
make it an ideal clock source for 10 Gigabit Ethernet,
SONET, and Serial Attached SCSI applications.
IC
S
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
32 31 30 29 28 27 26 25
M5
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
VCO_SEL
nP_LOAD
P
IN
A
SSIGNMENT
0
1
M4
M3
M2
M1
M0
XTAL_IN
24
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
1
÷
N
÷
1
÷
2
÷
4
÷
8
M6
M7
M8
FOUT0
nFOUT0
FOUT1
nFOUT1
N0
N1
nc
V
EE
ICS84320I-01
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
23
22
21
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84320AYI-01
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 11, 2005
Integrated
Circuit
Systems, Inc.
ICS84320I-01
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
matically occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relation-ship between
the VCO frequency, the crystal frequency and the M divider is
defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 25
≤
M
≤
31. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS84320I-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 620MHz to 780MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84320I-01 support two
input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial.
Figure 1
shows
the timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next
LOW transition on nP_LOAD or until a serial event occurs. As a
result, the M and N bits can be hardwired to set the M divider
and N output divider to a specific default state that will auto-
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
T0
H
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S_LOAD
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
84320AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 11, 2005
Integrated
Circuit
Systems, Inc.
ICS84320I-01
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Unused
Power
Output
Power
Output
Power
Output
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of
Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
17
MR
Input
Pulldown
18
19
20
21
22
23
24, 25
26
27
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_OUT,
XTAL_IN
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84320AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A AUGUST 11, 2005
Integrated
Circuit
Systems, Inc.
ICS84320I-01
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
X
X
L
L
↑
↓
L
H
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
625
•
700
•
M Divide
25
•
28
•
256
M8
0
•
0
•
128
M7
0
•
0
•
64
M6
0
•
0
•
32
M5
0
•
0
•
16
M4
1
•
1
•
8
M3
1
•
1
•
4
M2
0
•
1
•
2
M1
0
•
0
•
1
M0
1
•
0
•
1
775
31
0
0
0
0
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
620
310
155
77.5
Maximum
780
390
195
97.5
84320AYI-01
www.icst.com/products/hiperclocks.html
4
REV. A AUGUST 11, 2005
Integrated
Circuit
Systems, Inc.
ICS84320I-01
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
22
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
Parameter
Input
High Voltage
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
TEST_CLK
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
TEST_CLK
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
M5, XTAL_SEL, VCO_SEL
V
OH
V
OL
Output
High Voltage
Output
Low Voltage
TEST; NOTE 1
TEST; NOTE 1
Test Conditions
Minimum
2
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Input
Low Current
-150
2. 6
0.5
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
/2.
84320AYI-01
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 11, 2005
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