0
R
XC2C64 CoolRunner-II CPLD
0
0
DS092 (v1.2) May 13, 2002
Advance Product Specification
Features
•
Optimized for 1.8V systems
- As fast as 4.0 ns pin-to-pin logic delays
- As low as 15
µA
quiescent current
- 64 macrocells with up to 1,600 logic gates
- Fast input registers
- Slew rate control on individual outputs
- LVCMOS 1.8V through 3.3V
- 1.5V I/O compatible
- LVTTL 3.3V
Available in multiple package options
- 44-pin PLCC with 33 user I/O
- 44-pin VQFP with 33 user I/O
- 56-ball CP BGA with 45 user I/O
- 100-pin VQFP with 64 user I/O
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Fast Zero Power™ (FZP) 100% CMOS product
term generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
- Hot pluggable
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "fast input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asyncho-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see
Table 1).
This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
•
•
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS092 (v1.2) May 13, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
XC2C64 CoolRunner-II CPLD
R
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
Fast Zero Power™ (FZP), a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Table 1:
I/O Standards for XC2C64
Output
V
CCIO
3.3
3.3
2.5
1.8
1.5
Input
V
CCIO
3.3
3.3
2.5
1.8
1.5
Board
Input Termination
V
REF
Voltage V
T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O Types
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
Table 1
for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
20
-5, -7.5
15
ICC (mA)
10
5
0
0
50
100
150
200
250
300
DS092_01_030102
Frequency (MHz)
Figure 1:
I
CC
vs Frequency
Table 2:
I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
0
Typical -5, -7.5 I
CC
(mA)
Typical -4 I
CC
(mA)
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
25
1.85
50
3.69
75
5.55
100
7.35
150
10.87
175
12.54
200
14.22
225
15.91
250
17.56
270
18.9
0.015
2
www.xilinx.com
1-800-255-7778
DS092 (v1.2) May 13, 2002
Advance Product Specification
R
XC2C64 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
CCIO
V
JTAG
V
AUX
V
IN
V
TS
T
STG
T
SOL
T
J
Description
Supply voltage relative to ground
Supply voltage for output drivers
JTAG input voltage limits
JTAG input supply voltage
Input voltage relative to ground
(1)
Voltage applied to 3-state output
(1)
Storage Temperature (ambient)
Maximum Soldering temperature (10s @ 1/16in. = 1.5mm)
Junction Temperature
Value
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–65 to +150
+260
+150
Units
V
V
V
V
V
V
°C
°C
°C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
Recommended Operating Conditions
Symbol
V
CC
V
CCIO
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0°C to +70°C
Industrial T
A
= –40°C to +85°C
Min
1.7
1.7
3.0
2.3
1.7
1.4
1.7
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
V
V
V
V
V
V
V
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
V
AUX
JTAG programming pins
DC Electrical Characteristics
(Over Recommended Operating Conditions)
Symbol
I
CCSB
I
CCSB
I
CC
I
CC
C
JTAG
C
CLK
C
IO
Parameter
Standby current (-5, -7)
Standby current (-4)
Dynamic current (-5, -7)
Dynamic current (-4)
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Test Conditions
V
CC
= 1.9V, V
CCIO
= 3.6V
V
CC
= 1.9V, V
CCIO
= 3.6V
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min.
Max.
100
Units
µA
mA
mA
mA
mA
mA
pF
pF
pF
DS092 (v1.2) May 13, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
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