530AA360M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> 530AA360M000DGR

530AA360M000DGR: DescriptionStandard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS); CategoryPassive components; File Size1MB，12 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

530AA360M000DGR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	530AA360M000DGR	-	-	View	Buy Now

530AA360M000DGR Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)

530AA360M000DGR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Standard Clock Oscillators
Frequency	360 MHz
Frequency Stability	61.5 PPM
Load Capacitance	15 pF
Operating Supply Voltage	3.3 V
Supply Voltage - Min	2.97 V
Supply Voltage - Max	3.63 V
Output Format	LVPECL
Termination Style	SMD/SMT
Package / Case	5 mm x 7 mm
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Length	7 mm
Width	5 mm
Height	1.65 mm
Packaging	Box
Current Rating	111 mA
Type	Crystal Oscillator
Duty Cycle - Max	55 %

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Z T O

1 . 4 GH

)

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications



SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

GND

CLK+

Si530 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

CLK–

GND

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.4 5/13

Si530/531

Recommended Resources

Small capacitance and long duration timer circuit diagram

24V power supply using integrated block 05

LM723 high precision regulated power supply

MP3 circuit diagram high definition 2

Oxygen inhaler circuit

MCU logic operation: ANL A,Rn 58~5F AND register to A ANL A,direct 55 direct AND direct byte to A ANL A,@Ri 56~57 Indirect RAm to A ANL A,#data 54 AND data immediate to A ANL direct A 52 direct AND A to direct byteANL dir...; LS9001 51mcu

EE also detected unsafe issues, is that true?: The following prompt appears when using Google browser:...; dontium Talking

Quartus II Modelsim co-simulation problem: When performing a co-simulation with Quartus II and Modelsim, if the testbench content is changed, does synthesis need to be performed every time, or will Modelsim perform the synthesis itself when Mo...; luooove FPGA/CPLD

I want to switch to IC and I am looking for a job. Please give me some advice. Thank you.: Please help me : I am looking for a job across majors and industries this time. I know it is very difficult, but I really don't want to work in the previous industry. I studied chemical engineering in...; strorn Talking about work

【Guess the topic with prizes】Guess the topic of this year’s TI provincial competition?: The list of components for this year's TI League has already been released. For those who haven't seen it yet, please read the following post: List of instruments, equipment and main components for th...; okhxyyo Electronics Design Contest

How does the bottom layer receive messages from the application layer?: I sent a message from the bottom layer to the application layer (sendmessage). After the application layer processes it, I want to send a message to the bottom layer. How do I send it? How does the bo...; liede Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components