Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
F
EATURES
• Two HSTL outputs (VOHmax = 1.5V)
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS8421002I-01 is a 2 output HSTL
Synthesizer optimized to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz,
18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The
ICS8421002I-01 uses ICS’ 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typi-
cal r ms phase jitter, easily meeting Ether net jitter
requirements. The ICS8421002I-01 is packaged in a small
20-pin TSSOP package.
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
M Divider
Value
25
25
25
not used
N Divider
Value
4
5
10
Output Frequency
(25MHz Ref.)
156.25
125
62.5
not used
P
IN
A
SSIGNMENT
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
F_SEL1 F_SEL0
0
0
1
1
0
1
0
1
ICS8421002I-01
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
REF_CLK
Pulldown
25MHz
2
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
F_SEL[1:0]
0 0 ÷4
(default)
1
01
10
11
÷5
÷10
Not Used
1
nQ0
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
Q1
nQ1
0
M = 25 (fixed)
MR
Pulldown
8421002AGI-01
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 6, 2006
Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
Type
Description
No connect.
Output supply pins.
Differential output pair. HSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. HSTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
DDO
Q0, nQ0
MR
Unused
Power
Ouput
Input
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
nPLL_SEL
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
REF_CLK
nXTAL_SEL
GND
nQ1, Q1
Input
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
8421002AGI-01
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 6, 2006
Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
110
12
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
96
12
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 1.8V±0.2V,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465
or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
-150
µA
8421002AGI-01
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 6, 2006
Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.5
0.5
60
1. 3
Units
V
V
%
V
T
ABLE
3D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
OX
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
3E. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
OX
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
0.8
0
40
0.5
Typical
Maximum
1.5
0.6
60
1. 5
Units
V
V
%
V
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
22.4
Test Conditions
Minimum
Typical
25
Maximum
27.2
50
7
1
Units
MH z
Ω
pF
mW
Fundamental
8421002AGI-01
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 6, 2006
Integrated
Circuit
Systems, Inc.
ICS8421002I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
140
11 2
56
0.44
0.48
0.49
215
815
52
Typical
Maximum
170
136
68
20
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20% to 80%
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
odc
Output Duty Cycle
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20% to 80%
315
0.41
0.49
0.50
715
52
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
14 0
11 2
56
Typical
Maximum
170
136
68
20
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2 Please refer to the Phase Noise Plot.
NOTE 3 This parameter is defined in accordance with JEDEC Standard 65.
8421002AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 6, 2006
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