Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
™ 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
•
Output frequency range: 70MHz to 680MHz
•
Crystal input frequency range: 12MHz to 32MHz
•
VCO range: 560MHz to 680MHz
•
Parallel or serial interface for programming feedback
and output dividers
•
Input P_DIV under parallel load control
•
RMS phase jitter at 156.25MHz (1.875MHz to 20MHz):
0.49ps (typical), P_DIV =
÷1
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS843020-01 is a general purpose, dual out-
put Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™
quency Synthesizer and a member of the
FemtoClocks™ family of High Performance Clock
Solutions from ICS. The ICS843020-01 is based
rd
on ICS’ 3 generation VCO technology and is capable of sub-
1ps RMS Phase Jitter performance, making it ideal for use in
10 Gigabit Ethernet, 10 Gigabit Fibre Channel, SONET and
Serial ATA applications.
ICS
The ICS843020-01 is a highly flexible programmable synthe-
sizer capable of generating output frequencies over a range of
70MHz to 680MHz. The output frequency can be programmed
in small step sizes as low as 250kHz when using a 16MHz
crystal,
÷8
input divider, and output divider =
÷8.
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
P_DIV
÷
P
0
÷8
Float
÷1
(default)
1
÷4
1
0
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
32 31 30 29 28 27 26 25
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
M4
PLL
PHASE DETECTOR
MR
÷
M
VCO
0
1
÷
N
÷
1
÷
2
÷
4
÷
8
N0
N1
P_DIV
FOUT0
nFOUT0
FOUT1
nFOUT1
V
EE
ICS843020-01
M3
M2
M1
M0
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
843020AY-01
www.icst.com/products/hiperclocks.html
1
REV. B APRIL 14, 2005
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
™ 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
default state that will automatically occur during power-up. The
TEST output is LOW when operating in the parallel input mode.
The relation-ship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
fVCO = fxtal x M
P
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23
≤
M
≤
27 (P =
÷1).
The
frequency out is defined as follows:
FOUT = fVCO = fxtal x M
N
NxP
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS843020-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 560MHz to 680MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS843020-01 supports either serial or parallel program-
ming modes to program the M feedback divider and N output
divider. The input divider P can only be changed using the P_DIV
pin. It cannot be changed from the default
÷1
setting using the
serial interface.
Figure 1
shows the timing diagram for each mode.
In parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly to
the M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
S
t
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1, P_DIV
M, N, P
nP_LOAD
t
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
The NULL timing slot must be observed.
843020AY-01
www.icst.com/products/hiperclocks.html
2
REV. B APRIL 14, 2005
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
™ 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of
Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11, 12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
P_DIV
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
Pullup/
Input divide select. 0 = ÷8, Float =
÷
1 (default), 1 = ÷4.
Pulldown
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
affect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between cr ystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
17
MR
Input
Pulldown
18
19
20
21
22
23
24, 25
26
27
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_OUT,
XTAL_IN
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
843020AY-01
www.icst.com/products/hiperclocks.html
3
REV. B APRIL 14, 2005
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
™ 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
X
X
L
L
↑
↓
L
H
X
X
X
↑
L
L
X
↑
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD S_CLOCK
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
575
•
600
•
M Divide
23
•
24
•
256
M8
0
•
0
•
128
M7
0
•
0
•
64
M6
0
•
0
•
WITH
P =
÷
1 (P_DIV = F
LOAT
)
32
M5
0
•
0
•
16
M4
1
•
1
•
8
M3
0
•
1
•
4
M2
1
•
0
•
2
M1
1
•
0
•
1
M0
1
•
0
•
1
675
27
0
0
0
0
1
1
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
575
•
600
•
M Divide
92
•
96
•
256
M8
0
•
0
•
128
M7
0
•
0
•
64
M6
1
•
1
•
WITH
P =
÷
4 (P_DIV = 1)
32
M5
0
•
1
•
16
M4
1
•
0
•
8
M3
1
•
0
•
4
M2
1
•
0
•
2
M1
0
•
0
•
1
M0
0
•
0
•
0
675
108
0
0
1
1
0
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
www.icst.com/products/hiperclocks.html
4
843020AY-01
REV. B APRIL 14, 2005
Integrated
Circuit
Systems, Inc.
ICS843020-01
F
EMTO
C
LOCKS
™ 680MH
Z
, C
RYSTAL
-
TO
-
3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
WITH
T
ABLE
3D. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
575
•
600
•
M Divide
184
•
192
•
256
M8
0
•
0
•
128
M7
1
•
1
•
64
M6
0
•
1
•
P =
÷
8 (P_DIV = 0)
32
M5
1
•
0
•
16
M4
1
•
0
•
8
M3
1
•
0
•
4
M2
0
•
0
•
2
M1
0
•
0
•
1
M0
0
•
0
•
0
675
216
0
1
1
0
0
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
T
ABLE
3E. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
560
280
140
70
Maximum
680
340
170
85
843020AY-01
www.icst.com/products/hiperclocks.html
5
REV. B APRIL 14, 2005
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