PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844001I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
F
EATURES
•
(1) Differential LVDS output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
•
Output frequency range: 81.66MHz - 226.66MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.74ps (typical)
•
3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS844001I is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from ICS.
The ICS844001I uses an 18pF parallel resonant
crystal over the range of 20.4MHz - 28.3MHz.
For Fibre Channel applications, a 26.5625MHz crystal is used.
The frequency select pin allows the device to generate
either 106.25MHz or 212.5MHz from a 26.5625MHz
cr ystal. To generate 187.5MHz for 12Gb Ethernet, a
23.4375MHz crystal is used. The ICS844001I uses ICS’ 3
rd
generation low phase noise VCO technology and can
achieve <1ps typical rms phase jitter, easily meeting Fibre
Channel and Ethernet jitter requirements. The ICS844001I is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
ICS
C
OMMON
C
ONFIGURATION
T
ABLE
- F
IBRE
C
HANNEL
, 12Gb E
THERNET
Inputs
Crystal Frequency (MHz)
26.5625
26.5625
23.4375
FREQ_SEL
0
1
1
M
24
24
24
N
6
3
3
Multiplication
Value M/N
4
8
8
Output Frequency
(MHz)
106.25
212.5
187.5
B
LOCK
D
IAGRAM
FREQ_SEL
Pullup
P
IN
A
SSIGNMENT
÷3
1
Q
nQ
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
÷6
M = ÷24
(fixed)
0
ICS844001I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844001I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
Type
Power
Power
Input
Input
Pullup
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Frequency select pin.
Differential clock outputs. LVDS interface levels.
Core supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
FREQ_SEL
nQ, Q
V
DD
Output
Power
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
844001AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 16, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844001I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
TBD
TBD
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
FREQ_SEL
FREQ_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.25
50
Maximum
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
844001AGI
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 16, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844001I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
Test Conditions
Minimum
Typical
350
40
1.25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
20.4
Test Conditions
Minimum
Typical
Fundamental
28.3
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
106.25MHz @ Integration Range:
637kHz - 10MHz
187.5MHz @ Integration Range:
637kHz - 10MHz
212.5MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
Test Conditions
Minimum
81.66
0.74
0.48
0.70
260
50
Typical
Maximum
226.66
Units
MHz
ps
ps
ps
ps
%
t
jit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
t
R
/ t
F
Output Rise/Fall Time
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
106.25MHz @ Integration Range:
637kHz - 10MHz
187.5MHz @ Integration Range:
637kHz - 10MHz
212.5MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
Test Conditions
Minimum
81.66
0.97
0.58
0.95
260
50
Typical
Maximum
226.66
Units
MHz
ps
ps
ps
ps
%
t
jit(Ø)
RMS Phase Jitter ( Random);
NOTE 1
t
R
/ t
F
Output Rise/Fall Time
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
844001AGI
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 16, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844001I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Qx
3.3V±5%
POWER SUPPLY
+
Float GND
-
SCOPE
2.5V±5%
POWER SUPPLY
Qx
+
Float GND
-
SCOPE
LVDS
nQx
LVDS
nQx
LVDS 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Plot
LVDS 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQ
Noise Power
Q
t
PW
Phase Noise Mask
t
PERIOD
odc =
f
1
Offset Frequency
f
2
t
PW
t
PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
DD
V
DD
out
80%
Clock
Outputs
80%
V
SW I N G
➤
DC Input
LVDS
out
➤
20%
t
R
t
F
20%
➤
V
OS
/Δ V
OS
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DD
V
DD
➤
O
FFSET
V
OLTAGE
S
ETUP
out
DC Input
LVDS
➤
100
V
OD
/Δ V
OD
out
➤
REV. A JUNE 16, 2005
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
844001AGI
www.icst.com/products/hiperclocks.html
5
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