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BS62LV1027SCP55

Description
128K X 8 STANDARD SRAM, 55 ns, PDSO32
Categorystorage   
File Size387KB,11 Pages
ManufacturerBSI
Websitehttp://www.brilliancesemi.com/
Download Datasheet Parametric View All

BS62LV1027SCP55 Overview

128K X 8 STANDARD SRAM, 55 ns, PDSO32

BS62LV1027SCP55 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals32
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage3 V
Rated supply voltage5 V
maximum access time55 ns
Processing package description0.450 INCH, PLASTIC, ROHS COMPLIANT, SOP-32
Lead-freeYes
EU RoHS regulationsYes
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingNOT SPECIFIED
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
memory width8
organize128K × 8
storage density1.05E6 deg
operating modeASYNCHRONOUS
Number of digits131072 words
Number of digits128K
Memory IC typeStandard memory
serial parallelparallel
Very Low Power CMOS SRAM
128K X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV1027
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V Operation current : 18mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.02uA (Typ.) at 25
O
C
V
CC
= 5.0V Operation current : 47mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 0.4uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
:
3.0~5.5V
-70
70ns (Max.) at V
CC
:
2.7~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE2, CE1 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.02uA at 3.0V/25
O
C and maximum access time of 55ns at
3.0V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm STSOP,
8mmx20mm TSOP and 36-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV1027DC
BS62LV1027HC
BS62LV1027PC
BS62LV1027SC
BS62LV1027STC
BS62LV1027TC
BS62LV1027HI
BS62LV1027PI
BS62LV1027SI
BS62LV1027STI
BS62LV1027TI
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max.)
Operating
(I
CC
, Max.)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
Commercial
+0
O
C to +70
O
C
3.0uA
1.0uA
9mA
29mA
46mA
1.5mA
9mA
17mA
Industrial
-40
O
C to +85
O
C
5.0uA
1.5uA
10mA
30mA
47mA
2mA
10mA
18mA
DICE
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
n
PIN CONFIGURATIONS
n
BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
BS62LV1027STC
BS62LV1027STI
BS62LV1027TC
BS62LV1027TI
1
2
A1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 1024
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
128
Column Decoder
7
Control
Address Input Buffer
8
Column I/O
Write Driver
Sense Amp
3
CE2
4
A3
5
A6
6
A8
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV1027PC
BS62LV1027PI
BS62LV1027SC
BS62LV1027SI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
8
A
A0
Data
Output
Buffer
B
DQ4
A2
WE
A4
A7
DQ0
C
DQ5
NC
A5
DQ1
D
VSS
VCC
E
VCC
VSS
F
DQ6
NC
NC
DQ2
CE2
CE1
WE
OE
V
CC
GND
A5 A10 A4 A3 A2 A1 A0
G
DQ7
OE
CE1
A16
A15
DQ3
H
A9
A10
A11
A12
A13
A14
36-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV1027
1
Revision 2.3
May.
2006
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