Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
F
EATURES
•
9 differential 3.3V LVPECL / ECL outputs
•
1 differential LVPECL input pair
•
PLCK, nPLCK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: >2GHz (typical)
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•
Additive phase jitter, RMS: 0.03ps (typical)
•
Output skew: 35ps (maximum)
•
Part-to-part skew: 300ps (maximum)
•
Propagation delay: 675ps (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS853111-01 is a low skew, high perfor-
mance 1-to-9 Differential-to-3.3V LVPECL/ECL
HiPerClockS™
Fa n o u t B u f fe r a n d a m e m b e r o f t h e
HiPerClock S ™ family of High Performance
Clock Solutions from ICS. The PCLK, nPCLK
pair can accept LVPECL, CML and SSTL differential input
levels. The ICS853111-01 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS853111-01 ideal for
those clock distribution applications demanding well
defined performance and repeatability.
ICS
B
LOCK
D
IAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
V
BB
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
P
IN
A
SSIGNMENT
V
CCO
nQ0
nQ1
nQ2
Q0
Q1
Q2
25
V
EE
nc
PCLK
V
CC
nPCLK
V
BB
nc
26
27
28
1
2
3
4
5
nQ8
24
23
22
21
20
19
18
17
16
Q3
nQ3
Q4
V
CCO
nQ4
Q5
nQ5
ICS853111-01
15
14
13
12
6
Q8
7
nQ7
8
V
CCO
9
Q7
10
nQ6
11
Q6
REV. A APRIL 25, 2005
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
853111AV-01
www.icst.com/products/hiperclocks.html
1
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
Type
Description
Core supply pin.
Pullup/
Inver ting differential LVPECL clock input. Bias to V
CC
/2 w/no input.
Pulldown
1
Bias voltage.
No connect.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Pulldown
Non-inver ting differential LVPECL clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4, 27
5, 6
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
28
Name
V
CC
nPCLK
V
BB
nc
nQ8, Q8
nQ7, Q7
V
CCO
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
V
EE
PCLK
Power
Input
Output
Unused
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Power
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
PULLDOWN1
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input Pulldown Resistor
50
75
50
Test Conditions
Minimum
Typical
Maximum
1
Units
pF
KΩ
KΩ
KΩ
853111AV-01
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 25, 2005
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (LVECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V + 0.5 V
CC
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(LVECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
37.8°C/W (0 lfpm)
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
3A. LVPECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
V
CCO
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.8
3.8
75
Units
V
V
mA
Table 3B. LVPECL DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
-40°C
Min
2.175
1.405
2.075
1.43
1.86
150
1.2
800
25°C
Max
2.38
1.68
2.36
1.765
1.98
1200
3.3
150
85°C
Max
2.37
1.615
2.36
1.765
1.98
Typ
2.275
1.545
Min
2.225
1.425
2.075
1.43
1.86
150
1.2
Typ
2.295
1.52
Min
2.295
1.44
2.075
1.43
1.86
150
1.2
Typ
2.33
1.535
Max
2.365
1.63
2.36
1.765
1.98
Units
V
V
V
V
V
V
V
µA
µA
800
1200
3.3
150
800
1200
3.3
150
Input
-150
-150
-150
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853111AV-01
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 25, 2005
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
Test Conditions
Minimum
-3.0
Typical
-3.3
55
Maximum
-3.8
Units
V
mA
T
ABLE
3C. ECL P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3V
TO
-3.8V
Symbol
V
EE
I
EE
Parameter
Supply Voltage
Power Supply Current
Table 3D. ECL DC Characteristics,
V
CC
= 0V; V
EE
= -3V to -3.8V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
-40°C
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
25°C
Max
-0.92
-1.62
-0.94
-1.535
-1.32
1200
0
150
85°C
Max
-0.93
-1.685
-0.94
-1.535
-1.32
Typ
-1.025
-1.755
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-1.005
-1.78
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-0.97
-1.765
Max
-0.935
-1.67
-0.94
-1.535
-1.32
Units
V
V
V
V
V
V
V
µA
µA
800
1200
0
150
800
1200
0
150
Input
-150
-150
-150
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 3V
TO
3.8V; V
EE
= 0V
OR
V
CC
= 0V; V
EE
= -3V
TO
-3.8V
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
20% to 80%
90
-40°C
Min
Typ
>2
350
450
50 0
600
20
650
750
35
200
0.03
20 0
315
100
0.03
203
310
95
385
480
Max
Min
25°C
Typ
>2
525
620
20
675
760
35
200
0.03
210
300
410
515
Max
Mi n
85°C
Typ
>2
350
650
20
700
785
35
200
Max
Units
GH z
ps
ps
ps
ps
ps
ps
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
All parameters measured at f
≤
1GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111AV-01
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 25, 2005
Integrated
Circuit
Systems, Inc.
ICS853111-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL/ECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive
Phase Jitter
at 155.52MHz
= 0.03ps (typical)
SSB P
HASE
N
OISE
dBc/H
Z
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853111AV-01
www.icst.com/products/hiperclocks.html
5
REV. A APRIL 25, 2005
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