595CE61M4400DG datasheet, PDF - EEWORLD Datasheet

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595CE61M4400DG: DescriptionVCXO Oscillators VCXO; Diff/SE; Single Freq; 10-810 MHz; CategoryPassive components; File Size288KB，15 Pages; ManufacturerSilicon Laboratories

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595CE61M4400DG Overview

VCXO Oscillators VCXO; Diff/SE; Single Freq; 10-810 MHz

595CE61M4400DG Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	VCXO Oscillators
Packaging	Tray

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EVISION

Si595

O L TAG E

- C

ONTR OLLED

RYSTAL

S C I L L A T O R

(VCXO)

810 MH

Features

Available with any-rate output

frequencies from 10 to 810 MHz



3rd generation DSPLL

with

superior jitter performance



Internal fixed fundamental mode

crystal frequency ensures high

reliability and low aging



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry standard 5x7 and

3.2x5 mm packages

Pb-free/RoHS-compliant

–40 to +85 ºC operating range

Si5602

Applications



Ordering Information:



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video

FTTx

Clock recovery and jitter cleanup PLLs

FPGA/ASIC clock generation

See page 8.

Pin Assignments:

See page 7.

(Top View)

GND

CLK–

CLK+

Description

The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to

provide a low-jitter clock at high frequencies. The Si595 is available with

any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs,

where a different crystal is required for each output frequency, the Si595

uses one fixed crystal to provide a wide range of output frequencies. This IC-

based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides supply noise rejection, simplifying the task of generating low-jitter

clocks in noisy environments. The Si595 IC-based VCXO is factory-

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, tuning slope, and absolute pull range (APR).

Specific configurations are factory programmed at time of shipment, thereby

eliminating the long lead times associated with custom oscillators.

Functional Block Diagram

CLK–

CLK+

Fixed

Frequency

Any-rate

10–810 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 1.3 12/17

Si595

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