Product Specification
PE9313
Product Description
The PE9313 is a high-performance static UltraCMOS™
prescaler with a fixed divide ratio of 8. Its operating frequency
range is DC to 1500 MHz. The PE9313 operates on a nominal
3 V supply and draws only 6.5 mA. It is packaged in a small 8-
lead ceramic SOIC and is ideal for frequency scaling and clock
generation solutions.
The PE9313 is manufactured in Peregrine’s patented Ultra-
Thin Silicon (UTSi®) CMOS process, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
1500 MHz Low Power UltraCMOS™
Divide-by-8 Prescaler
Rad hard for Space Applications
Features
•
DC to 1500 MHz operation
•
Fixed divide ratio of 8
•
Low-power operation: 6.5 mA typical
@3V
•
Ultra small package: 8-lead Ceramic
SOIC
•
Guaranteed 100Krads(Si) Total Dose
Performance
•
Superior Single Event Upset Immunity
Figure 1. Functional Diagram
Figure 2. Package Type
8-lead CSOIC
D
IN
Pre-Amp
Q
D
Q
D
Q
OUT
Output
Buffer
CLK QB
CLK QB
CLK QB
Table 1. Electrical Specifications @ +25 °C, V
DD
= 2.6 V
(Z
S
= Z
L
= 50
Ω)
V
DD
= 3.0 V, -40° C
≤
T
A
≤
85° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Input Frequency (F
in
)
Conditions
Minimum
2.85
Typical
3.0
6.5
Maximum
3.15
11
1500
+10
+10
Units
V
mA
MHz
dBm
dBm
dBm
DC
DC <
Fin
•
1000 MHz
-8
0
0
Input Power (P
in
)
1000 <
Fin
•
1500 MHz
Output Power (P
out
)
DC < Fin
•
1500 MHz
Document No. 70-0120-02
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www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
PE9313
Product Specification
Figure 3. Pin Configuration
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
V
DD
1
2
8
7
GND
IN
OUT
PE9313
N/C
3
4
6
5
NC
GND
GND
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
Pin
Name
V
DD
IN
NC
GND
GND
NC
Device Functional Considerations
Description
Power supply pin. Bypassing is required
(eg 1000 pF & 100 pF).
Input signal pin. Should be coupled with a
capacitor (eg 1000 pF).
No connection. This pin should be left
open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
No connection. This pin should be left
open.
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg 1000 pF).
Ground Pin.
The
PE9313
divides an input signal, up to a
frequency of 1500 MHz, by a factor of eight
thereby producing an output frequency at an
eighth of the input frequency. To work properly at
higher frequency, the input and output signals
(pins 2 & 7) must be AC coupled via an external
capacitor, as shown in the test circuit in Figure 8.
The input may be DC coupled for low frequency
operation with care taken to remain within the
specified DC input range for the device.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 7 for a layout example.
7
8
OUT
GND
Table 3. Absolute Maximum Ratings
Symbol
V
DD
P
in
V
IN
T
ST
T
OP
V
ESD
Parameter/Conditions
Supply voltage
Input Power
Voltage on input
Storage temperature range
Operating temperature
ESD voltage (Human Body
Model, MIL-STD 883)
Min
Max
4.0
15
Units
V
dBm
V
°C
°C
V
-0.3
-65
-40
1000
V
DD
+0.3
150
85
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0120-02
│
UltraCMOS™ RFIC Solutions
PE9313
Product Specification
Typical Performance Data: V
DD
= 3.0 V
Figure 4. Input Sensitivity
Figure 5. Device Current
Figure 6. Output Power
Document No. 70-0120-02
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 7
PE9313
Product Specification
Figure 7. Test Circuit Block Diagram
3V
100 pF
1000 pF
VDD
GND
50
IN
1000pF
N/C
OUT
1000pF
N/C
50
Power Meter or
Frequency Counter
GND
GND
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0120-02
│
UltraCMOS™ RFIC Solutions
PE9313
Product Specification
Evaluation Kit Operation
The Ceramic SOIC Prescaler Evaluation Board was
designed to help customers evaluate the
PE9313
divide-by-8 prescaler. On this board, the device
input (pin 2) is connected to the SMA connector J1
through a 50
Ω
transmission line. A series capacitor
(C3) provides the necessary DC block for the device
input. A value of 1000 pF was used for the
evaluation board; other applications may require a
different value. It is also possible to place a 0
Ω
resistor in this location for very low frequency
applications.
The device output (pin 7) is connected to SMA
connector J3 through a 50
Ω
transmission line. A
series capacitor (C1) provides the necessary DC
block for the device output. This capacitor value
must be chosen to have a low impedance at the
desired output frequency of the device. A value of
1000 pF was chosen for the evaluation board.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane model with trace
width of 0.030”, trace gaps of 0.0061”, dielectric
thickness of 0.028”, metal thickness of 0.0014”, and
ε
r
of 4.6. Note that the predominate mode of these
transmission lines is coplanar waveguide.
J2 provides DC power to the device via pin 1. Two
decoupling capacitors (C2=100 pF, C10=1000 pF)
are included on this trace. It is the responsibility of
the customer to determine proper supply decoupling
for their design application.
Figure 8. Evaluation Board Layout
Peregrine specification 102/0034
Figure 9. Evaluation Board Schematic
Peregrine specification 102/0202
Document No. 70-0120-02
│
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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