Product Specification
PE9354
Product Description
The PE9354 SPDT High Power UltraCMOS™ RF Switch is
designed to cover a broad range of applications from near DC
to 3000 MHz. This single-supply reflective switch integrates on-
board CMOS control logic driven by a simple, single-pin CMOS
and TTL compatible control input. Using a nominal +3-volt
power supply, a typical input 1 dB compression point of +31
dBm can be achieved. The PE9354 also exhibits input-output
isolation of better than 30 dB at 2000 MHz and is offered in a
small 8-lead ceramic SOIC package.
The PE9354 is optimized for commercial space applications.
Single Event Latch up (SEL) is physically impossible and
Single Event Upset (SEU) is better than 10-9 errors per bit/day.
Fabricated in Peregrine’s UltraCMOS™ technology, the
PE9354 offers excellent RF performance and intrinsic radiation
tolerance.
Figure 1. Functional Schematic Diagram
RFC
SPDT High Power
UltraCMOS™ RF Switch
Rad hard for Space Applications
Features
•
Single 3-volt power supply
•
Low insertion loss: 0.55 dB at 2000 MHz
•
High isolation of 30 dB at 2000 MHz
•
Typical input 1 dB compression point of
+31 dBm
•
100 Krad total dose
•
Single-pin CMOS or TTL logic control
•
Low cost
Figure 2. Package Type
8-lead CSOIC
RF1
RF2
CMOS
Control
Driver
CTRL
Table 1. A/C Electrical Specifications -55 °C to +125 °C, V
DD
= 3.0 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operation Frequency
1
Insertion Loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return Loss
2
Input 1 dB Compression
2000 MHz
2000 MHz
2000 MHz
2000 MHz
2000 MHz
28
28
24
Conditions
Minimum
DC
Typical
Maximum
3000
Units
MHz
dB
dB
dB
dB
dBm
0.55
32
28
22
31
0.80
Note: 1. Device linearity will begin to degrade below 10 MHz.
Note: 2. Return loss not measured in production due to equipment limitations
Document No. 70-0099-02
│
www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 7
PE9354
Product Specification
Figure 3. Pin Configuration
V
DD
CTRL
GND
1
2
8
7
RF1
GND
GND
RF2
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
CTRL
Parameter/Conditions
Power supply voltage
Voltage on any input
except for the CTRL input
Voltage on CTRL input
Storage temperature range
Operating temperature
range
Input power (50
Ω)
ESD voltage (Human Body
Model)
Total Cumulative Exposure
to Ionizing Radiation
Min
-0.3
-0.3
Max
4.0
V
DD
+
0.3
5.0
150
125
32
200
100k
Units
V
V
V
°C
°C
dBm
V
Rads
(Si)
PE9354
3
4
6
5
T
ST
T
OP
-65
-55
RFC
P
IN
V
ESD
Table 2. Pin Descriptions
Pin
No.
1
Total Dose
Pin
Name
V
DD
Description
Nominal +3V supply connection.
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
physically short and connected to
ground plane for best performance.
Common RF port for switch.
1
RF2 port.
1
Ground Connection. Traces should be
physically short and connected to
ground plane for best performance.
Ground Connection. Traces should be
physically short and connected to
ground plane for best performance.
RF1 port.
1
2
CTRL
3
4
5
6
GND
RFC
RF2
GND
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
7
8
GND
RF1
Note 1: All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
Table 4. DC Electrical Specifications
Parameter
V
DD
Power Supply
Voltage
Input Leakage
I
DD
Power Supply
Current
(V
DD
= 3V, V
CNTL
= 3V)
Control Voltage High
Control Voltage Low
0.7xV
DD
0.3xV
DD
Min
2.7
-1
Typ
3.0
Max
3.3
1
Units
V
µA
µA
V
V
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFC to RF1
RFC to RF2
28
100
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0099-02
│
UltraCMOS™ RFIC Solutions
PE9354
Product Specification
Typical Performance Data
@ -55 °C to 125 °C
Figure 4. Insertion Loss – RFC to RF1
Figure 5. Input 1dB Compression Point
Figure 6. Insertion Loss – RFC to RF2
Figure 7. Isolation – RFC to RF1
Document No. 70-0099-02
│
www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 7
PE9354
Product Specification
Typical Performance Data
@ -55 °C to 125 °C
Figure 8. Isolation – RFC to RF2
Figure 9. Isolation – RF1/RF2 to RF2/RF1
Figure 10. Return Loss – RFC
Figure 11. Return Loss – RF1, RF2
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 7
Document No. 70-0099-02
│
UltraCMOS™ RFIC Solutions
PE9354
Product Specification
Evaluation Kit Information
Evaluation Kit
The SPDT Switch Evaluation Kit board was designed to
ease customer evaluation of the
PE9354
SPDT switch.
The RF common port is connected through a 50
Ω
transmission line to the top left SMA connector, J1.
Port 1 and Port 2 are connected through 50
Ω
transmission lines to the top two SMA connectors on
the right side of the board, J2 and J3. A through
transmission line connects SMA connectors J4 and J5.
This transmission line can be used to estimate the loss
of the PCB over the environmental conditions being
evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a coplanar
waveguide with ground plane model using a trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CNTL input. The fourth pin to the right (J2-7) is
connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
The ground plane has been removed from beneath the
device for performance issues. It was found that
insertion loss dips (suck-outs) were experienced due to
the capacitive effect of the metal package sitting
insulated by the solder-mask on the ground plane. All
Figure
12. Evaluation Board Layouts
data specified and shown on this datasheet was taken
using this evaluation board configuration. For optimal
performance, the package may be soldered directly to
the ground plane, but the reliability issues associated
with this mounting must be addressed by the customer.
Figure
13. Evaluation Board Schematic
Peregrine specification 102/0129
Document No. 70-0099-02
│
www.psemi.com
©2004-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 7
Robotics Development
京公网安备 11010802033920号
EEWORLD
