STB180N55
STP180N55
N-CHANNEL 55V - 2.9mΩ - 120A - D²PAK - TO-220
MDmesh™ Low Voltage Power MOSFET
TARGET SPECIFICATION
General features
Type
STB180N55
STP180N55
■
■
V
DSS
55V
55V
R
DS(on)
3.5mΩ
3.8mΩ
I
D
120A (Note 1)
120A (Note 1)
3
1
1
2
3
ULTRA LOW ON-RESISTANCE
100% AVALANCHE TESTED
D²PAK
TO-220
Description
This N-Channel enhancement mode MOSFET is
the latest refinement of STMicroelectronic unique
“Single Feature Size™“ strip-based process with
less critical aligment steps and therefore a
remarkable manufacturing reproducibility. The
resulting transistor shows extremely high packing
density for low on-resistance, rugged avalanche
characteristics and low gate charge
.
Internal schematic diagram
Applications
■
HIGH CURRENT SWITCHING APPLICATION
Order codes
Sales Type
STB180N55
STP180N55
Marking
B180N55
P180N55
Package
D²PAK
TO-220
Packaging
TAPE & REEL
TUBE
January 2006
This is a preliminary information on a new product foreseen to be developed. Details are subject to change without notice
Rev 1
1/11
www.st.com
11
1 Electrical ratings
STP180N55 - STB180N55
1
Table 1.
Electrical ratings
Absolute maximum ratings
Parameter
Drain-source Voltage (V
GS
=0)
Gate-Source Voltage
Drain Current (continuous) at T
C
= 25°C
Drain Current (continuous) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
dv/dt
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
Operating Junction Temperature
Storage Temperature
Value
55
± 20
120
120
480
315
2.1
TBD
TBD
-55 to 175
Unit
V
V
A
A
A
W
W/°C
V/ns
mJ
°C
Symbol
V
DS
V
GS
I
D
Note
1
I
D
Note
1
I
DM
Note
2
P
TOT
E
AS
Note
4
T
j
T
stg
Table 2.
Thermal data
TO-220
D²PAK
0.48
62.5
--
300
--
35
--
Unit
°C/W
°C/W
°C/W
°C
Rthj-case
Rthj-a
Rthj-pcb
Note
5
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering
Purpose
2/11
STP180N55 - STB180N55
2 Electrical characteristics
2
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 3.
Symbol
V
(BR)DSS
I
DSS
On/off states
Parameter
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current (V
GS
= 0)
Gate Body Leakage Current
(V
DS
= 0)
Gate Threshold Voltage
Static Drain-Source On
Resistance
Test Conditions
I
D
= 250µA, V
GS
= 0
V
DS
= Max Rating,
V
DS
= Max Rating,Tc = 125°C
V
GS
= ±20V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 60A
D²PAK
TO-220
2
Min.
55
10
100
±
200
Typ.
Max.
Unit
V
µA
µA
nA
V
mΩ
mΩ
I
GSS
V
GS(th)
R
DS(on)
4
3.5
3.8
Table 4.
Symbol
g
fs
Note
3
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
Dynamic
Parameter
Forward Transconductance
Test Conditions
V
DS
=15V, I
D
= 60A
Min.
Typ.
TBD
6200
1800
100
110
TBD
TBD
TBD
Max.
Unit
S
pF
pF
pF
nC
nC
nC
Input Capacitance
V
DS
=25V, f=1 MHz, V
GS
=0
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=44V, I
D
= 120A
V
GS
=10V
(see Figure 2)
3/11
2 Electrical characteristics
STP180N55 - STB180N55
Table 5.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on Delay Time
Rise Time
Test Conditions
V
DD
=27V, I
D
= 60A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 3)
V
DD
=27V, I
D
= 60A,
R
G
=4.7Ω, V
GS
=10V
(see Figure 3)
Min.
Typ.
TBD
TBD
Max.
Unit
ns
ns
Off voltage Rise Time
FallTime
TBD
TBD
ns
ns
Table 6.
Symbol
I
SD
I
SDM
Note
2
V
SD
Note
3
t
rr
Q
rr
I
RRM
Source drain diode
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
=120A, V
GS
=0
I
SD
=120A, di/dt = 100A/µs,
V
DD
=30V, Tj=150°C
TBD
TBD
TBD
Test Conditions
Min.
Typ.
Max.
120
480
1.5
Unit
A
A
V
ns
nC
A
(1) Current limited by package
(2) Pulse width limited by safe operating area
(3) Pulsed: pulse duration = 300µs, duty cycle 1.5%
(4) Starting Tj=25°C, Id=60A, Vdd=40V
(5) When mounted o inch² FR4 2oz Cu
4/11
STP180N55 - STB180N55
3 Test circuits
3
Test circuits
Switching Times Test Circuit For
Resistive Load
Figure 2.
Gate Charge Test Circuit
Figure 1.
Figure 3.
Test Circuit For Indictive Load
Switching and Diode Recovery
Times
Figure 5.
Unclamped Inductive Load Test
Circuit
Figure 4.
Unclamped Inductive Waveform
Figure 6.
Switching Time Waveform
5/11
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