Semiconductor
MSC23V47257TD-xxBS18
DESCRIPTION
This version: Apr. 22. 1999
Previous version: Apr. 1. 1999
4,194,304-Word x 72-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
The MSC23V47257TD-xxBS18 is a 4,194,304-word x 72-bit CMOS dynamic random access memory module which
is composed of eighteen 16Mb(4Mx4) DRAMs in TSOP packages mounted with eighteen decoupling capacitors.
This is an 168-pin dual in-line memory module. This module supports any application where high density and large
capacity of storage memory are required.
FEATURES
· 4,194,304-word x 72-bit organization
· 168-pin Dual In-line Memory Module
· Gold tab
· Single 3.3V power supply, ±0.3V tolerance
· Input
: LVTTL compatible
· Output
: LVTTL compatible, 3-state
· Refresh : 2048cycles/ 32ms
· /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
· Fast page mode with EDO, read modify write capability
· Multi-bit test mode capability
· Serial Presence Detect
PRODUCT FAMILY
Access Time (Max.)
t
RAC
MSC23V47257TD-50BS18
MSC23V47257TD-60BS18
MSC23V47257TD-70BS18
50ns
60ns
70ns
t
AA
25ns
30ns
35ns
t
CAC
13ns
15ns
20ns
t
OEA
13ns
15ns
20ns
Cycle
Time
(Min.)
84ns
104ns
124ns
Power Dissipation (Max.)
Operating
6480mW
5832mW
5184mW
32.4mW
Standby
Family
Semiconductor
MSC23V47257TD
Serial PD Matrix
SPD Value
(Hex)
80
08
02
0B
0B
01
48
00
01
32
/RAS Access Time
3C
46
0D
/CAS Access Time
0F
14
DIMM Configuration type
Refresh Rate/Type
Primary DRAM Width
Error Checking DRAM Width
Superset Information
SPD Data Revision Code
-50
63
-60
-70
64-127
128-255
Reserved
Unused Storage Location (Reserved)
Checksum for Byte 0-62
02
00
04
04
00
01
34
40
4F
00
FF
128 Bytes
256 Bytes
EDO
11
11
1
72
0
LVTTL
50ns
60ns
70ns
13ns
15ns
20ns
ECC
Normal Refresh
x4
x4
Reserved
1
Byte No.
0
1
2
3
4
5
6
7
8
-50
9
-60
-70
-50
10
-60
-70
11
12
13
14
15-61
62
Function described
Number of Byte used
Total SPD Memory size
Memory type
Number of Rows
Number of Columns
Number of Banks
Module Data Width
Module Data Width Continued
Supply Voltage
Note