Si53212/Si53208/Si53204 Data Sheet
12/8/4-Output PCI-Express Low Jitter, Low Power Gen 1/2/3/4
SRIS Clock Buffer
The Si53212, Si53208, and Si53204 are the industry’s highest performance, low additive
jitter, low power PCIe clock fanout buffer family that can source 12, 8, or 4 100 MHz
PCIe clock outputs. All differential clock outputs are compliant to PCIe Gen1/2/3/4 com-
mon clock and separate reference clock specifications. This family of buffers is spread
spectrum tolerant to pass through a spread input clock. Each device has an individual
hardware output enable control pin for enabling and disabling each differential output.
Other than 100 MHz, the device can also support input frequencies from 10 MHz to 200
MHz. All the devices are packaged in small QFN packages. The small footprint and low-
power consumption make this family of PCIe clock fanout buffers ideal for industrial and
consumer applications. To confirm PCI-Express compliance, the Silicon Labs PCIe
Clock Jitter Tool makes measuring PCIe clock jitter quick and easy. Download it for free
at
http://www.silabs.com/pcie-learningcenter.
Applications
• Data Centers
• Servers
• Storage
• PCIe Add-on Cards
• Communications
• Industrial
KEY FEATURES
• 12/8/4-output 100 MHz PCIe Gen1/2/3/4
and SRIS compliant clock fanout buffer
• Low-power, push-pull, HCSL compatible
differential outputs
• 10 MHz to 200 MHz clock input
• Spread spectrum tolerant to pass through
a spread input clock for EMI reduction
• Supports Intel QPI/UPI standards
• Single 1.5 to 1.8 V power supply
• 85 Ω and 100 Ω termination ordering
options
• Temperature range: –40 °C to 85 °C
• Package options:
• 64-pin QFN (9 x 9 mm) : 12-output
• 48-pin QFN (6 x 6 mm) : 8-output
• 32-pin QFN (5 x 5 mm) : 4-output
• Small QFN packages
• Pb-free, RoHS-6 compliant
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.7
Si53212/Si53208/Si53204 Data Sheet
Feature List
1. Feature List
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12/8/4-output 100 MHz PCIe Gen1/2/3/4 and SRIS compliant clock fanout buffer
Low-power, push-pull, HCSL compatible differential outputs 10 MHz to 200 MHz clock input
Spread spectrum tolerant to pass through a spread input clock for EMI reduction
Supports Intel QPI/UPI jitter requirements with margin
Internal 100 Ω and 85 Ω output termination
• Eliminates external termination resistors to reduce board space
Single 1.5–1.8 V power supply
Temperature range: –40°C to 85°C
Package options:
• 64-pin QFN (9 x 9 mm), 12-output
• 48-pin QFN (6 x 6 mm), 8-output
• 32-pin QFN (5 x 5 mm), 4-output
Pb-free, RoHS-6 compliant
•
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Preliminary Rev. 0.7 | 2
Si53212/Si53208/Si53204 Data Sheet
Ordering Guide
2. Ordering Guide
Number of Outputs
12-output
Internal Termination
100 Ω
Part Number
Si53212-A01AGM
Si53212-A01AGMR
85 Ω
Si53212-A02AGM
Si53212-A02AGMR
8-output
100 Ω
Si53208-A01AGM
Si53208-A01AGMR
85 Ω
Si53208-A02AGM
Si53208-A02AGMR
4-output
100 Ω
Si53204-A01AGM
Si53204-A01AGMR
85 Ω
Si53204-A02AGM
Si53204-A02AGMR
2.1 Technical Support
Table 2.1. Technical Support URLs
https://www.silabs.com/community/timing/knowledge-base.entry.html/2018/02/26/
si532xx_si53204_si53-LO33
http://www.silabs.com/Si532xx-FAQ
PCIe Clock Jitter Tool
PCIe Learning Center
Development Kit
www.silabs.com/products/timing/pci-express-learning-center
www.silabs.com/products/timing/pci-express-learning-center
https://www.silabs.com/products/development-tools/timing/clock-buffer/si53208-evaluation-
kit.html
Package Type
64-QFN
64-QFN, Tape and Reel
64-QFN
64-QFN, Tape and Reel
48-QFN
48-QFN, Tape and Reel
48-QFN
48-QFN, Tape and Reel
32-QFN
32-QFN, Tape and Reel
32-QFN
32-QFN, Tape and Reel
Temperature
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85°C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Frequently Asked Questions
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Preliminary Rev. 0.7 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
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. 3
2.1 Technical Support
3. Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 OEb Pin .
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5.2 OEb Assertion .
12
.12
.12
.12
5.3 OEb Deassertion .
6. Test and Measurement Setup
7. PCIe Clock Jitter Tool
8. Pin Descriptions
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.16
.19
.21
8.1 Si53212 Pin Descriptions .
8.2 Si53208 Pin Descriptions .
8.3 Si53204 Pin Descriptions .
9. Packaging
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.23
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9.1 Si53212 Package.
9.3 Si53208 Package.
9.5 Si53204 Package.
9.2 Si53212 Land Pattern .
9.4 Si53208 Land Pattern .
9.6 Si53204 Land Pattern .
9.7 Si53212 Top Markings .
9.8 Si53208 Top Markings .
9.9 Si53204 Top Markings .
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
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Preliminary Rev. 0.7 | 4
Si53212/Si53208/Si53204 Data Sheet
Functional Block Diagrams
3. Functional Block Diagrams
Si53212
CLKIN
DIFF[11:0]
CLKINb
OEb[11:0]
PWRGD/PWRDNb
Figure 3.1. Si53212 Block Diagram
Si53208
CLKIN
DIFF[7:0]
CLKINb
OEb[7:0]
PWRGD/PWRDNb
Figure 3.2. Si53208 Block Diagram
Si53204
CLKIN
DIFF[3:0]
CLKINb
OEb[3:0]
PWRGD/PWRDNb
Figure 3.3. Si53204 Block Diagram
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Preliminary Rev. 0.7 | 5