Semiconductor
MR53V8052J
524,288-Word X 16-Bit or 1,048,576-Word X 8-Bit
8Word X 16-Bit or 16Word X 8-Bit/Page Mode MASK ROM
This version: Feb. 1999
Previous version: -------
Preliminary
DESCRIPTION
The MR53V8052J is a 8Mbit Read-Only Memory whose configuration can be electrically switched
between 524,288 word x 16bit and 1,048,576 word x 8bit. The MR53V8052J operates asynchronously,
external clocks are not required, making this device easy-to-use. The MR53V8052J is suitable as
large-capacity fixed memory for microcomputers and data terminals. It is manufactured using a CMOS
silicon gate technology and is offered in 42-pin DIP, 44-pin SOP or 44-pin TSOP packages.
FEATURES
· 524,288 word x 16bit / 1,048,576 word x 8bit electrically switchable configuration
· 8word x 16-Bit or 16word x 8-bit / Page read mode
· Single +2.7V~3.6V power supply
· Normal access time
· Page access time
· V
CC
power supply current
· V
CC
standby current
· Three-state output
· Packages
42-pin plastic DIP
44-pin plastic SOP
(DIP42-P-600-2.54)
(SOP44-P-600-1.27-K)
MR53V8052J-XXRA
MR53V8052J-XXMA
100ns
30ns
80mA
10mA
· Input / Output TTL compatible
44-pin plastic TSOP (TSOPII44-P-400-0.80-K) MR53V8052J-XXTP
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Semiconductor
MR53V8052J
BLOCK DIAGRAM
A-1
BYTE
X8/X16 SWITCH
CE
OE
CE
OE
CONTROL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Row
Decoder
Address
Buffer
Memory Cell
Matrix
524,288 x 16 or 1,048,676 x 8
Column
Decoder
Multiplexer
Output Buffer
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
FUNCTION TABLE
MODE
STAND BY
OUTPUT DISABLE
READ(16-BIT)
READ(8-BIT)
CE
H
L
L
L
L
OE
X
H
H
L
L
BYTE
X
H
L
H
L
D0~D7
D8~D14
Hi-Z
D
OUT
Hi-Z
L/H
L/H
A-1/D15
D
OUT
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Semiconductor
MR53V8052J
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Symbol
T
OPR
T
STG
V
I
V
O
V
CC
P
D
Condition
-
-
Relative to V
SS
-
Value
0 ~ 70
-55 ~ 125
-0.5 ~ V
CC
+0.5
-0.5 ~ V
CC
+0.5
-0.5 ~ 5
1.0
Unit
`C
`C
V
V
V
W
RECOMMENDED OPERATING CONDITIONS FOR READ
Parameter
V
CC
power supply voltage
Input “H“ level
Input “L“ level
Voltage is relative to V
SS
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
=2.7V ~ 3.6V
Min.
2.7
2.2
-0.5
Typ.
-
-
-
(Ta=0 ~ 70`C)
Min.
Unit
3.6
`C
V
CC
+0.5
`C
0.8
V
PIN Capacitance
Parameter
Input
Output
Symbol
C
IN
C
OUT
Condition
V
I
=0V
V
O
=0V
(Vcc=3.3V, Ta=25`C, f=1MHz)
Min.
Typ.
Min.
Unit
-
-
12
pF
-
-
15
pF
4/6
Semiconductor
MR53V8052J
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Input leakage current
Output leakage current
V
CC
power supply current
(Standby)
V
CC
power supply current
(Active)
Input “H“ level
Input “L“ level
Output “H“ level
Output “L“ level
Voltage is relative to V
SS
AC Characteristics
Symbol
C
IN
C
OUT
I
CCSC
I
CCST
I
CCA
V
IH
V
IL
V
OH
V
OL
Condition
V
I
=0V~V
CC
V
O
=0V~V
CC
CE= V
CC
CE= V
IH
CE= V
IL
, OE= V
IH
tc= 100ns
-
-
I
OH
=-200
mA
I
OL
=1mA
(Vcc=2.7V~3.6V, Ta=0~70`C)
Min.
Typ.
Min.
Unit
-
-
10
mA
-
-
10
mA
-
-
10
mA
-
-
1
mA
-
2.0
-0.5
V
CC
-0.4
-
-
-
-
-
-
80
V
CC
+0.5
0.8
-
0.4
mA
V
V
V
V
(Vcc=2.7V~3.6V, Ta=0~70`C)
Parameter
Symbol
Condition
Min.
Min.
Unit
Address access cycle time
T
C
-
100
-
ns
Address access time
T
ACC
CE=OE= V
IL
-
100
ns
Page set up time
T
PSET
NOTE.1
100
-
ns
Page access cycle time
T
PC
-
30
-
ns
Page access time
T
PAC
-
-
30
ns
CE access time
T
CE
OE= V
IL
-
100
ns
OE access time
T
OE
CE= V
IL
-
30
ns
Output disable time
T
CHZ
OE= V
IL
0
30
ns
T
OHZ
CE= V
IL
0
25
ns
Output hold time
T
OH
CE=OE= V
IL
0
-
ns
NOTE.1 T
PSET
is defined as the end of either CE falling edge or address transition in random access
term until the first page address transition.
Measurement condition
Input signal level
Input timing reference level
Output load
Output timing reference level
1.7V
0V/3V
0.8V/2.0V
100pF
0.8V/2.0V
400W
Output
100pF
5/6
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