Datasheet
2.7V to 5.5V Input, 5.0A Integrated MOSFET
Single Synchronous Buck DC/DC Converter
BD9B500MUV
General Description
BD9B500MUV is a synchronous buck switching
regulator with built-in low on-resistance power MOSFETs.
This IC, which is capable of providing current up to 5A,
features fast transient response by employing constant
on-time control system. It offers high oscillating
frequency at low inductance. With its original constant
on-time control method which operates low consumption
at light load, this product is ideal for equipment and
devices that demand minimal standby power
consumption.
Key Specifications
Input Voltage Range:
2.7V to 5.5V
Output Voltage Range:
0.8 V to V
PVIN
x 0.8 V
Maximum Operating Current:
5A (Max)
Switching Frequency:
2MHz/1MHz (Typ)
High-Side MOSFET ON Resistance: 30mΩ (Typ)
Low-Side MOSFET ON Resistance: 30mΩ (Typ)
Standby Current:
0μA (Typ)
W (Typ) x D (Typ) x H (Max)
3.00 mm x 3.00 mm x 1.00 mm
Package(s)
VQFN016V3030
Features
Synchronous single DC/DC Converter
Constant on-time control suitable to Deep-SLLM
Over Current Protection
Short Circuit Protection
Thermal Shutdown Protection
Under Voltage Lockout Protection
Adjustable Soft Start
Power Good Output
VQFN016V3030 Package
(backside heat dissipation)
VQFN016V3030
Applications
Step-down Power Supply for DSPs, FPGAs,
Microprocessors, etc.
Laptop PCs/Tablet PCs/Servers
LCD TVs
Storage Devices (HDDs/SSDs)
Printers, OA Equipment
Entertainment Devices
Distributed Power Supply, Secondary Power Supply
Typical Application Circuit
VIN
BD9B500MUV
PVIN
PGD
AVIN
Enable
22µF
0.1µF
AGND
PGND
SS
MODE
C
SS
FREQ
FB
R2
R1
C
FB
22µF×2
SW
1.0µH
EN
BOOT
0.1µF
V
OUT
PGD
Figure 1. Application Circuit
〇Product
structure : Silicon monolithic integrated circuit
.
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〇This
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Pin Configuration(s)
(TOP VIEW)
BOOT
13
12
11
AVIN
16
15
PVIN
PVIN
PGND
PGND
PGD
14
EN
1
2
SW
SW
SW
SS
E-Pad
3
4
10
9
5
6
7
8
AGND
FB
Figure 2. Pin Assignment
Pin Description(s)
Pin No.
1, 2
3, 4
5
6
Pin Name
PVIN
PGND
AGND
FB
Function
Power supply terminals for the switching regulator.
These terminals supply power to the output stage of the switching regulator.
Connecting a 22µF ceramic capacitor is recommended.
Ground terminals for the output stage of the switching regulator.
Ground terminal for the control circuit.
An inverting input node for the error amplifier and main comparator.
See page 22 for how to calculate the resistance of the output voltage setting.
Terminal for setting switching frequency. Connecting this terminal to ground makes
switching to operate constant on-time corresponding to 2.0MHz. Connecting this
terminal to AVIN makes switching to operate constant on-time corresponding to
1.0MHz. Please fix this terminal to AVIN or ground in operation.
Terminal for setting switching control mode. Connecting this terminal to AVIN forces
the device to operate in the fixed frequency PWM mode. Connecting this terminal to
ground enables the Deep-SLLM control and the mode is automatically switched
between the Deep-SLLM control and fixed frequency PWM mode. Please fix this
terminal to AVIN or ground in operation.
Terminal for setting the soft start time. The rise time of the output voltage can be
specified by connecting a capacitor to this terminal. See page 23 for how to calculate
the capacitance.
Switch nodes. These terminals are connected to the source of the High-Side
MOSFET and drain of the Low-Side MOSFET. Connect a bootstrap capacitor of 0.1µF
between these terminals and BOOT terminal. In addition, connect an inductor of
0.47µH to 1.0µH (FREQ=L), 1.0μH to 1.5μH (FREQ=H) considering the direct current
superimposition characteristic.
Terminal for bootstrap. Connect a bootstrap capacitor of 0.1µF between this terminal
and SW terminals. The voltage of this terminal is the gate drive voltage of the
High-Side MOSFET.
A “Power Good” terminal, an open drain output. Use of pull up resistor is needed. See
page 17 for how to specify the resistance. When the FB terminal voltage reaches
more than 80% of 0.8 V, the internal Nch MOSFET turns off and the output turns High.
Enable terminal. Turning this terminal signal Low (0.8V or lower) forces the device to
enter the shutdown mode. Turning this terminal signal High (2.0V or higher) enables
the device. This terminal must be terminated.
Terminal for supplying power to the control circuit of the switching regulator.
Connecting a 0.1µF ceramic capacitor is recommended.
This terminal must be connected to PVIN.
A backside heat dissipation exposed pad. Connecting to the internal PCB ground
plane by using multiple vias provides excellent heat dissipation characteristics.
7
FREQ
8
MODE
9
SS
10, 11, 12
SW
13
BOOT
14
PGD
15
EN
16
AVIN
-
E-Pad
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MODE
FREQ
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Block Diagram(s)
AVIN
16
1
2
HOCP
LOCP
SCP
13
PVIN
EN
15
UVLO
FB
BOOT
6
Error
Amplifier
Main
Comparator
On Time
Modulation
SS
9
Soft Start
On Time
Control
Logic
+
DRV
10
11
12
SW
VOUT
VREF
PGND
PGOOD
TSD
3
4
5
AGND
PGD
14
7
FREQ
8
MODE
Figure 3. Block Diagram
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Description of Block(s)
●
VREF
The VREF block generates the internal reference voltage.
UVLO
The UVLO block is for Under Voltage Lockout protection. It will shut down the IC when VIN falls to 2.45V (Typ) or
lower. The threshold voltage has a hysteresis of 100mV (Typ).
TSD
The TSD block is for thermal protection. The thermal protection circuit shuts down the device when the internal
temperature of IC rises to 175°C (Typ) or higher. Thermal protection circuit resets when the temperature falls. The
circuit has a hysteresis of 25°C (Typ).
Soft Start
The Soft Start circuit slows down the rise of output voltage during start-up and controls the current, which allows the
prevention of output voltage overshoot and inrush current. A built-in soft start function is provided and a soft start is
initiated in 1msec (Typ) when the SS terminal is open.
Control Logic + DRV
This block is a DC/DC driver. A signal from On Time is applied to drive the MOSFETs.
PGOOD
When the FB terminal voltage reaches more than 80% of 0.8V, the Nch MOSFET of the built-in open drain output
turns off and the output turns High.
HOCP/LOCP/SCP
After soft start is completed and in condition where output voltage is below 70% (Typ) of voltage setting, it counts the
number of times of which current flowing in High side FET or Low side FET reaches over current limit. When 512
times is counted it stops operation for 1msec (Typ) and re-operates. Counting is reset when output voltage is above
80% (Typ) of voltage setting or when EN, UVLO, SCP function is re-operated.
Error Amplifier
Adjusts Main Comparator input to make internal reference voltage equal to FB terminal voltage.
Main Comparator
Main comparator compares Error Amplifier output and FB terminal voltage. When FB terminal voltage becomes low it
outputs High and reports to the On Time block that the output voltage has dropped below control voltage.
On Time
This is a block which creates On Time. Desired On Time is created when Main Comparator output becomes High.
On Time is adjusted to restrict frequency change even with I/O voltage change.
●
●
●
●
●
●
●
●
●
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BD9B500MUV
Absolute Maximum Ratings (Ta = 25°C)
Parameter
Supply Voltage
EN Terminal Voltage
MODE Terminal Voltage
FREQ Terminal Voltage
PGD Terminal Voltage
Voltage from GND to BOOT
Voltage from SW to BOOT
FB Terminal Voltage
SW Terminal Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Symbol
V
PVIN
, V
AVIN
V
EN
V
MODE
V
FREQ
V
PGD
V
BOOT
⊿V
BOOT
V
FB
V
SW
I
OUT
Topr
Tstg
Rating
-0.3 to +7
-0.3 to +7
-0.3 to +7
-0.3 to +7
-0.3 to +7
-0.3 to +14
-0.3 to +7
-0.3 to +7
-0.3 to V
PVIN
+ 0.3
5.5
-40 to 85
-55 to 150
Unit
V
V
V
V
V
V
V
V
V
A
C
C
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated
over the absolute maximum ratings.
Thermal Resistance
(Note 1)
Parameter
VQFN016V3030
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
θ
JA
Ψ
JT
189.0
23
57.5
10
°C/W
°C/W
Symbol
Thermal Resistance (Typ)
1s
(Note 3)
2s2p
(Note
4)
Unit
(Note 1)Based
on JESD51-2A(Still-Air)
(Note 2)The
thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)Using
a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Single
Top
Copper Pattern
Footprints and Traces
Layer Number of
Measurement Board
4 Layers
Top
Copper Pattern
Footprints and Traces
Material
FR-4
Board Size
114.3mm x 76.2mm x 1.57mmt
Thickness
70μm
(Note 4)Using
a PCB board based on JESD51-5, 7.
Material
FR-4
Board Size
114.3mm x 76.2mm x 1.6mmt
2 Internal Layers
Thermal Via
(NOTE 5)
Pitch
1.20mm
Bottom
Copper Pattern
74.2mm x 74.2mm
Thickness
70μm
35μm
Diameter
Φ0.30mm
Thickness
70μm
Copper Pattern
74.2mm x 74.2mm
Thickness
(Note 5)
This thermal via connects with the copper pattern of all layers..
Recommended Operating Conditions
(Ta= -40°C to +85°C)
Parameter
Supply Voltage
Output Current
Output Voltage Range
Symbol
V
PVIN
, V
AVIN
I
OUT
V
RANGE
Min
2.7
-
0.8
Typ
-
-
-
Max
5.5
5.0
V
PVIN
× 0.8
Unit
V
A
V
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