Features
•
Advanced, High-Speed Programmable Logic Device-Superset of 22V10
– Improved Performance - 7.5 ns tPD, 95 MHz External Operation
– Enhanced Logic Flexibility
– Backward Compatible with ATV750/L Software and Hardware
•
New Flip-Flop Features
– D- or T-Type
– Product Term or Direct Input Pin Clocking
•
High-Speed Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
Device
ATV750B
ATV750BL
I
CC
, Stand-By
125 mA
15 mA
•
Highest Density Programmable Logic Available in a 24-Pin Package
•
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
•
Enhanced Output Logic Flexibility
– All 20 Flip-Flops Feed Back Internally
– 10 Flip-Flops are Also Available as Outputs
•
Full Military, Commercial and Industrial Temperature Ranges
High-Speed
UV-Erasable
Programmable
Logic Device
ATV750B
Logic Diagram
Description
The ATV750Bs are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform, predictable delays
guarantee fast in-system performance.
(continued)
Pin Configurations
Pin Name
CLK
IN
I/O
*
V
CC
Function
Clock
Logic Inputs
Bidirectional Buffers
No Internal Connection
+5V Supply
Rev. 0301D–05/98
DIP/SOIC
PLCC/LCC
Top View
1
Each of the ATV750B’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi-
directional I/O pins. Each flip-flop is individually config-
urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. A variable for-
mat is used to assign between four to eight product terms
per sum term. There are two sum terms per output, provid-
ing added flexibility. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu-
ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip-
flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power up.
The ATV750BL is a low power device with speeds as fast
as 15 ns. The ATV750BL provides the optimum low power
PLD solution, with full CMOS output levels. This device sig-
nificantly reduces total system power, thereby allowing bat-
tery-powered operation.
Abosute Maximum Rating*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Integrated UV Erase Dose..............................7258 W
•
sec/cm
2
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is V
CC
+ 0.75V DC which
may overshoot to +7.0V for pulses of less than 20
ns.
Logic Options
Combinatorial Output
Combined Terms
Separate Terms
Registered Output
Combined Terms
Separate Terms
2
ATV750B
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