ATV2500H-30PC datasheet, PDF - EEWORLD Datasheet

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ATV2500H-30PC: DescriptionHigh-Density UV-Erasable Programmable Logic Device; CategoryProgrammable logic devices Programmable logic; File Size458KB，15 Pages; ManufacturerAtmel (Microchip)

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ATV2500H-30PC Overview

High-Density UV-Erasable Programmable Logic Device

ATV2500H-30PC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	unknow
Other features	24 MACROCELLS
maximum clock frequency	33 MHz
In-system programmable	NO
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
JTAG BST	NO
length	52.2 mm
Dedicated input times	14
Number of I/O lines	24
Number of macro cells	24
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
organize	14 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	30 ns
Certification status	Not Qualified
Maximum seat height	5.59 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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Features

•

Third Generation Programmable Logic Structure

•

– Easily Achieves Gate Utilization Factors of 80 Percent

Increased Logic Flexibility

– 86 Inputs and 72 Sum Terms

Flexible Output Macrocell

– 48 Flip-Flops - 2 per Macrocell

– 3 Sum Terms - Can Be OR'ed and Shared

High-Speed

Low-Power — Less than 0.5 mA Typical (ATV2500L)

Multiple Feedback Paths Provide for Buried State Machines

and I/O Bus Compatibility

Asynchronous Clocks and Resets

– Multiple Synchronous Presets - One per Four or Eight Flip-Flops

Proven and Reliable High Speed CMOS EPROM Process

– 2000V ESD Protection

– 200 mA Latchup Immunity

Reprogrammable - Tested 100% for Programmability

40-pin Dual-In-line and 44-Lead Surface Mount Packages

High-Density

UV-Erasable

Programmable

Logic Device

ATV2500H

ATV2500L

Block Diagram

Description

The ATV2500H/L is the most powerful programmable logic device available in a 40-

pin package. Increased product terms, sum terms, and flip-flops translate into many

more usable gates. High gate utilization is easily obtainable.

The ATV2500H/L is organized around a global bus. All pin and feedback terms are

always available to every logic cell. Each of the 38 logic pins and their complements

are array inputs, as well as the true and false outputs of each of the 48 flip-flops.

(continued)

Pin Configurations

Pin Name

I/O

I/O, 0,2,4..

I/O, 1,3,5..

VCC

Function

Logic Inputs

Bidirectional Buffers

“Even” I/O Buffers

“Odd” I/O Buffers

No Internal Connection

+5V Supply

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

DIP

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

I/O19

I/O18

PLCC/LCC

I/O1

I/O0

I/O06

* = No Connect

Rev. 0025E–05/98

I/O12

I/O18

I/O19

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

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